Quantum Mechanical Electrostatics and Transport Simulation and Performance Evaluation of Short Channel Monolayer WSe2 Field Effect Transistor

Tuesday, 26 May 2015: 10:20
Lake Ontario (Hilton Chicago)
S. U. Z. Khan and Q. D. M. Khosru (Bangladesh University of Engineering and Technology)
To counter the performance degradation of extremely scaled FETs due to SCEs, ultrathin body channel material with high band gap is essential [1]. In recent years, researchers have been working on Graphene and monolayer transition metal dichalcogenides like MoS2, WSe2 to find the channel material for next generation ultimately scaled transistors. Although, Graphene fulfills the condition of thin body channel and it has excellent carrier mobility, the absence of intrinsic band gap in Graphene sheet made researchers focus on dichalcogenides like MoS2. Despite of showing promise for low power application, MoS2 based transistors are less suitable for high performance operation since monolayer MoS2 has a high electron and hole effective mass and low carrier mobility [2]. In search of high mobility monolayer channel material, many other transition metal dichalcogenides are being explored [3] and as a result of that endeavor monolayer WSe2 based pFET has been fabricated [1] . This experimental device with high band gap (1.6 eV) showed higher carrier mobility (250 cm2/Vs) than monolayer MoS2 based devices. In recent literature methods of n-type and p-type doping of monolayer WSe2 FET are demonstrated [4-5], which led to fabrication of high performance CMOS inverter solely based on monolayer WSe2 channel [6]. Despite of these promising experimental results, rigorous transport and electrostatic study of monolayer WSe2 based FET is yet to appear in the literature. In this work, we have performed a quantum mechanical electrostatics and transport simulation study on monolayer WSe2 FET and calculated different performance parameters.

The device structure considered in this work is the nFET version of the device fabricated by Fang et al. [1] which has a 0.7 nm thick monolayer WSe2 channel of length 9.4 μm deposited on a 270 nm thick layer of SiO2. A 17.5 nm thick layer of ZrO2 served as the top oxide of the device (Figure 1). To model the monolayer WSe2 channel FET, we used band structure and material parameters available in the literature from first principle DFT simulations of Monolayer WSe2 sheets which have been listed in table I.

In this work, 1D Schrodinger-Poisson equations have been solved self-consistently along the direction perpendicular to the channel to get the C-V characteristics of the device (Figure 2). Then, ballistic transport characteristics were obtained using Launder-Buttiker formulation. Figure 3 and 4 show the Id-Vds and transfer characteristics of the device respectively. The threshold voltage of the device was extracted as 1.1 V (Figure 5). The subthreshold slope was calculated to be 60.913 mV/dec (Figure 6), which is remarkably near to the theoretical lower limit of 60mv/dec.

Table II lists some of the performance parameters obtained from the transport simulation. The parameters indicates that monolayer WSe2 FET has a very high on-off current ratio (~108), which makes it suitable for low power applications. The threshold voltage is found to be 1.1V for this undoped monolayer WSe2 channel which can be tuned by changing doping profile and physical dimensions of the device.

In this work we have a developed a simulator to study the electrostatics and quantum transport of monolayer WSe2 FET and extracted the performance parameters of that device. The developed simulator can be extended to calculate the ultimate performance limit and study the effects of different physical parameter variation on the performance of the device.

[1] Fang et al, Nano letters, 12(7), pp. 3788-3792 (2012).

[2] Yoon et al., Nano letters, 11(9), pp. 3768–3773 (2011).

[3] Kang et al., IEDM’12, p. 407-410 (2012).

[4] Chen et al, APL Materials 2, p. 092504 (2014).

[5] Zhao et al., ACS Nano, 8 (10), pp 10808–10814 (2014).

[6] Tosun et al., ACS Nano, 8(5), pp. 4948–4953 (2014).

[7] Liu et al., ECS Transactions, 58 (7), pp. 281-285 (2013).

[8] Ghosh et al., IEEE JEDS, 1(10), pp. 175-180 (2013).