The Device-Perimeter Dependency in the Transient Current of a Metal-Insulator-Metal-Insulator-Semiconductor Capacitor with Anodic Oxide Films

Thursday, October 15, 2015: 15:40
103-A (Phoenix Convention Center)
C. S. Liao (National Taiwan University) and J. G. Hwu (National Taiwan University)
Capacitors are commonly used in semiconductor devices like gate capacitors of transistors, memory cells of dynamic random access memory (DRAM), and so on. In this work, a capacitor with electrochemically grown thin oxide films was fabricated as shown in figure 1. The Al2O3/Al/AlSixOy/SiO2 stack structure was formed by anodization as shown in figure 2. First, the SiO2 layer was formed by anodizing the surface of a p-type Si wafer as shown in figure 2(a). Next, a thin Al film was thermally deposited. Then, the Al2O3 layer was formed by partially anodizing the surface of the Al film as shown in figure 2(b). The sample was then annealed at 380°C in N2 ambient for 10 min, and an AlSixOy layer was formed between Al and SiO2. Three square device patterns, 150×150μm2 (sample D1), 300×300μm2 (sample D2), and 600×600μm2 (sample D3), of the Al electrodes were fabricated by thermal deposition and lithography.

     Figure 3 shows the gate current per device-area and per device-perimeter versus the gate voltage of the capacitor. Note that the currents merge at negative voltages in (a) while they merge at the saturation region in (b). It tells that the current flows uniformly across the whole area of the device at negative voltages while it flows along the device edge at the voltages in current saturation region due to the fringing field effect, which coincides with the results in the previous studies [1].

     Figure 4 shows the read currents of the capacitor at 0.1 V versus time after various negative and positive voltage pulses. The inset in (a) is the schematic diagram of the write and read processes settings. (b) is the read currents in (a) divided by the device perimeter. Note that the negative read currents merge in (a) while the positive read currents merge in (b). The charge in the sandwiched Al layer and the read current can be written as

Qg(t)=Qg(0)exp(–t/τ)                                  (1)

Ig(t)=dQg(t)/dt=–(Qg(0)/τ)exp(–t/τ)            (2)

where Qg(t) is the stored charge at time tτ is the time constant which is equal to RsCg. Rs is the total series resistance. Cg is the gate capacitance. The time constants extracted from figure 4 are all about 0.7 s. Qg(0) can be obtained by the write process as follows:

Qg(0)≈Qg(–t0)=∫(IwriteIleak)dt                  (3)

where Iwrite is the write current, Ileak is the leakage current during writing, and t0 is the switching time from write to read. While the write voltage is positive, the electrons flow from substrate to the sandwiched Al layer along the device edge due to the fringing field effect. However, the electrons also leak from the sandwiched Al layer to metal gate along the edge due to the thin oxide, and therefore Qg(0) is nearly independent of the device dimension. Hence, Ig(t) is independent of the device dimension. While the write voltage is negative, the stored electrons in the sandwiched Al layer were depleted due to the high negative gate field. When read at 0.1 V, the electrons were injected into the sandwiched Al layer along the edge due to the fringing field effect, and therefore Qg(0) is dependent on the device perimeter. Hence, Ig(t) is proportional to the device perimeter.

     The device-perimeter dependency in the current characteristics of the capacitor mentioned in this work might be useful for IC circuit design.

     This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. NSC 102-2221-E-002-183-MY3 and MOST 103-2622-E-002-031.

Figure Captions:

Figure 1. (a) The TEM cross-section and (b) the EDX line-scanning component analysis of the capacitor.

Figure 2. The schematic diagrams of (a) SiO2 anodization and (b) Al2O3 anodization processes for the capacitor fabrication.

Figure 3. (a) The gate current per device area and (b) the gate current per device perimeter versus gate voltage characteristics. Sample D1, D2, and D3 are the devices with square patterns of 150×150μm2, 300×300μm2, and 600×600μm2.

Figure 4. The currents read at 0.1 V versus time after the write processes. The inset in (a) shows the operation process. (b) is the read currents in (a) divided by the device perimeters.


[1]   H. W. Lu and J. G. Hwu, ECS Trans., 58, 339 (2013).