Critical BEOL Aspects of the Fabrication of a Thermally-Assisted MRAM Device

Recent developments in new switching methods, such as spin transfer torque [1] and temperature-assisted switching (TAS) [2], have greatly increased interest in MRAM. MRAM fabrication is challenging, however, due to the lack of magnetic materials processing experience by semiconductor lines. 

In this talk, we will discuss key back-end-of-line (BEOL) fabrication aspects for a CMOS-integrated thermally-assisted (TAS) MRAM on 200 mm wafers with, e.g., opens/shorts yields of 100% and 99% for 1Mb and 16 Mb arrays, resp. The cell sizes were 33F^2 for the 16M cell, and 73F^2 for the 1M cell, where F = 90 nm. This was achieved in our Microelectronics Research Laboratory (MRL) facility through careful process optimization and adherence to good BEOL processing practice.  Factors influencing opens and shorts yields will be discussed.  

In the TAS-MRAM magnetic tunnel junction (MTJ) device, data retention is enhanced through synthetic antiferromagnetic exchange coupling; during writing; coupling is overcome through passage of a heating current through the MTJ, and a lower switching field suffices to switch the heated device [2]. 

Figure 1 contains TEMs of a TAS MRAM structure with two dual-Damascene Cu levels and an Al level after the MTJ. The 90 nm base FEOL/BEOL CMOS technology wafers were fabricated by a third party. Fabrication at IBM commenced at V3, and trilayer via and trench RIE masking schemes were used below the final Al level. The field line (M4) had ferromagnetic (FM) cladding of either PVD Ni-Fe alloy or Co. Cladding proved challenging for narrow field lines (≤ 0.5 µm);  e.g., in the initial stages of Cu plating, imperfect  corner seedlayer coverage led to solution attack of the Co.

A Damascene TaN layer (ca. 50 nm thick) served as the pedestal for the MTJ. The MTJ resist mask patterns were trimmed using RIE to afford, after MTJ methanol-based RIE etching, final device sizes of about 110 nm.  After MTJ encapsulation with SiN and dielectric deposition, V4 vias were RIE etched, stopping on SiN. During M5 dielectric RIE, the MTJ pillar tops were exposed, and the V4 vias’ SiN cleared. The final V5/M6 Cu level was followed by an Al level. 

Besides the FM liner, other processing challenges included clearing isolated vias, and developing a robust trench RIE process to contact the MTJs. 

[1] J. C. Slonczewski, J. Magn. Magn. Mater.,159, L1 (1996).

[2] For example, I. L. Prejbeanu et al., J. Phys: Condens. Matter, 19 (16), 165218 (2007).

Acknowledgements:  Back-end-of-line fabrication was carried out in the Microelectronics Research Laboratory (MRL) at the T. J. Watson Research Center. The MRAM stacks were deposited at Crocus Technology in Grenoble, France.