Dummy Poly Gate Removal Process Optimization with Pulsing Plasma Application

Wednesday, October 14, 2015
West Hall 1 (Phoenix Convention Center)


The technology of High-K/metal gate has led to the continuity of device scaling and enabled the extension of Moore’s Law towards 28 nm node and beyond. The gate last approach has been widely adopted since it can better control n/p-MOS transistor threshold voltage (Vt), hence yielding better electrical performance [1]. However, it poses the formidable challenges to every process of metal gate formation, especially for the 2nd DPGR (dummy gate removal) process.  

In order to get the robust device performance, the 2nd-DPGR [2] process needs to fully consider all kinds of tangled aspects such as trench profile, n/p-MOS boundary interface, ILD (Interlayer dielectric) loss, Al damage, trench poly residue, trench corner residue, PID (plasmas induce damage), HK capping layer loss and surface residue. In this work, we will first introduce the various dilemma of the 2nd DPGR with conventional CW (continuous wave) plasma approach, and demonstrate the hybrid pulsing scheme could completely solve the aforementioned issues. Synchronous and source-only pulsing plasma have been introduced in the different etch steps of the 2nd DPGR. Synchronous pulsing scheme is proven to achieve vertical trench profile, clean n/p-MOS boundary, precisely-controlled oxide loss/Al damage. While, source-only pulsing PET (post etch treatment) is effective in terms of HK capping layer loss control without sacrificing the ability of interface treatment.

1.Trench Bottom Profile and n/p-MOS Boundary

Perfect trench profile could alleviate the gap-fill difficulty and deliver the more reliable device performance. In the 2nd DPGR process, too much profile pull-back at trench bottom is not acceptable. This necessitates the demand for extremely anisotropic dry etching. Besides, n/p-MOS boundary connects the pull -up area and the pull-down area, highly related to ring oscillation performance. As is well known, the produced etching polymer/by-product inevitably adheres to n/p-MOS boundary during DPGR for the high selectivity of poly-si over oxide is required to avoid the excessive oxide loss. However, such polymer/by-product needs to be fully removed before metal gap-fill. Seemingly, even if CW plasma could leverage the extra either in-situ step or ex-situ step to thin down such polymer/by product layer. However, we found there is a trade-off relationship between trench bottom profile and n/p-MOS boundary. On another side, pulsing plasma paves the way to seek the common process window for the above two targets. In synchronous pulsing plasma, the polymer/by-products could be pumped out easily during the plasma-off time and more positive charges could be neutralized at trench bottom. With the proper frequency and duty cycle, we achieved the vertical trench profile with clean n/p-MOS boundary as shown in Fig 1a and b.

2.ILD Loss, Al Damage and Poly Residue

In the 2nd DPGR process, the sufficient hard-mask OE (over-etch) process must be kept to avoid poly-Si residue at trench bottom. However, the excessive OE will induce serious Al damage and more ILD loss. The former could result in Al corrosion; the latter could tend to suffer n/p-MOS bridge risk because of metal residue after CMP (chemical mechanical polishing). Finally, we leveraged the synchronous pulsing scheme to tackle both issues from the point of view of less bombardment. 

3.Bottom Corner Residue and PID

HBr/O2, the typical silicon etch process, tends to suffer trench bottom corner residue. This could reduce the effective channel length, introduce process variation and worsen Vt mismatch. To solve this issue, we resorted to NF3/H2 gas combination to fully remove trench corner residue. However, the device test randomly shows PID issue. This might be the fact that H atom could easily damage HK oxide and/or its capping layer at higher electron temperature under CW plasma mode. Again, synchronous pulsing plasma can balance both corner residue and PID issue as it can reduce the averaged electron temperature to a very low level and the electron shading effect by neutralizing the electron accumulated at trench bottom.

4.Capping Layer Loss and Its Interface

HK capping layer is used to protect HK oxide from direct plasma bombardment. The thickness and surface roughness of capping layer are very critical to the adjustment of gate work function, leakage and reliability control. In this work, we came up with the source-only pulsing PET and have proven that it is capable of rigorously controlling capping layer loss without sacrificing the ability of interface treatment.


This work is partially sponsored by Shanghai Rising-Star Program (B type).

[1] P. Lim et al, USP, 7871915 B2 “Method for forming metal gates in a gate last process”, 2011

[2] Jack Huang, et al, SPIE, “Synchronous Pulsing Plasma Utilization in Dummy Poly Gate Removal Process”, 2015