The Effect of CoSi2 Formation Process on the CMOS Transistor Electrical Properties for Sub 100nm Memory Applications

We investigated the effect of various processing conditions on the abnormal CoSi2 formation, such as well-known Co spike and crystal phase agglomeration. We also focused on the effect of CoSi2 related defects on the electrical properties in real sub 100nm ULSI devices. The mechanism of electrical failure was proposed and employed to clarify the relation between the various process conditions and electrical properties of our ULSI chips.

We used the Co metal sputtering and next thermal treatment like RTP(rapid thermal process). The effect of ion implantation condition (dopant species and concentration) and different Co deposition methods (capping material and in-situ thermal treatment) has been studied. To evaluate the electrical failure of transistors, we tried to check the full chip level drain leakage current, which is represented by “DLC_chip”, and unit transistor level drain leakage current, which is called by “DLC_unit”, at the same time.

It was found that with varying dopant species and concentration, the source-drain junction depth, dopant spatial distribution and local electric field could change, which brought about the DLC(drain leakage current) phenomenon. And, since it is believed to affect the electrical property of every single transistor, DLC_chip and DLC_unit degrade or improve simultaneously.

The different deposition methods of Co material led to the changes in the characteristics of CoSix formation. When we used the Ti/TiN capping layer and hot temperature PVD, the abnormal growth was suppressed and the interface became smooth, which could prevent the agglomeration and Co spike. For electrical properties, the DLC_chip of both cases showed the significant improvement, however, the DLC_unit showed a negligible change or even degrade a little bit contrary to DLC_chip. We concluded that, in spite of the degradation of DLC(drain leakage current) in typical transistor, the overall level of DLC_chip has improved due to the significantly decreased amount of defective sites like abnormal growth. It was also proposed that the small amount of defective site was eligible to govern the chip level DLC and responsible for electrical failure of a single chip.