Low Doped n-type Localized Porous Silicon Made by Hole Injection from Back-side p+/n Junction for Power Switches Application

Monday, October 12, 2015: 14:50
102-B (Phoenix Convention Center)
A. Fèvre (ST Microelectronics, Tours, Université de Tours/GREMAN/CNRS/CEA/INSA-CVL), S. Menard (ST Microelectronics, Tours), T. Defforge (Université de Tours/GREMAN/CNRS/CEA/INSA-CVL), and G. Gautier (Université de Tours/GREMAN/CNRS/CEA/INSA-CVL)
Power switches are often present in electrical domestic environment directly connected to the mains supply. This kind of component operates in two principal modes, i.e. ON-mode and OFF-mode. The OFF-mode depends on the device periphery insulation capacity. Glass passivated grooves in the silicon are currently used giving good performances for reasonable cost. Changing this technology would permit higher wafer diameter and packaging simplification. Porous silicon (PS) is a potential candidate thanks to its electrical insulating behavior [1]. However, the usual substrate type and doping for such devices are n-type silicon and 1.1014 cm-3 respectively. At this doping level, porous silicon formation needs hole supply from an external source to avoid breakdown mechanism [1]. This can be achieved by either electron-hole pairs generation by illumination [2] or hole injection from a back-side p+/n junction [3][4]. This study focused on the second technique, which is easier to integrate in an industrial microelectronic process. Indeed, the presence in the active area (ON-mode) of a p+ region on the rear side could be used as a hole source. This junction is realized by boron implantation followed by an annealing. During the electrochemical etching, the p+/n junction needs to be forward biased to inject holes toward the anodic surface (Fig 1). Then, carrier lifetime must be sufficient to let holes cross n-type bulk silicon, featured by its thickness d (Fig 1).

First, a simplified case of non-localized p+/n junction is investigated (Fig 1). The influence of anodization parameters such as the current density and the electrolyte composition (additives) is presented for high HF concentration. A comparison with illumination technique is also discussed. Whatever the process case, the resulting PS morphology consists of a double layer (Fig 2): with a nucleation layer composed of mesopores and a macroporous layer filled with mesopores. To the best of our knowledge, this morphology has not been analyzed for low doped n-type silicon in the literature though it was mentioned in [5].

Electrical transverse characterization in DC (-10 to 10 V) of an Aluminum/PS/Si/Aluminum stack shows a gain in resistivity of 106Ω.cm compared to bulk silicon which is promising for the application.

As PS will be only present in the device periphery, a study of its localization is investigated. The resulting masking issues are analyzed.

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4. L. Coudron, G. Gautier, B. Morillon, S. Kouassi, T. Defforge and L. Ventura, Electrochem. and solid-state letters, 14, H24 (2011).

5. X.Q. Bao, D.H. Ge, S. Zhang, L. Zhao, J.W. Jiao and Y.L. Wang, Chinese Science Bulletin, 54 (7), 1143 (2009).