(Invited) Factors Impacting Threshold Voltage in Advanced CMOS Integration: Gate Last (FINFET) vs. Gate First (FDSOI)

Monday, October 12, 2015: 15:10
105-B (Phoenix Convention Center)
D. Triyoso, R. Carter, J. Kluth, S. Luning, A. Child, J. Wahl, B. Mulfinger, K. Punchihewa, A. Kumar, L. Kang, R. Sporer, X. Chen, S. Straub, G. Bohra, S. Patil, X. Zhang, A. Chen, M. Togo (GLOBALFOUNDRIES), and R. Pal (GLOBALFOUNDRIES)
After decades of research, high-k metal gate has been successfully integrated into CMOS starting with 45nm node.  High-k can be integrated using gate first or gate last integration.  To continue scaling, the industry has chosen two integration approaches: FINFET with gate last and FDSOI with gate first.  FINFET with gate last integration was introduced into production at 22nm node by Intel [1].  FDSOI with gate first integration was introduced into production at 28nm node by ST Microelectronics[2].  There are some common factors impacting threshold voltage (Vt) on both of these integrations such as high-k /metal gate film thickness and composition as well as doping concentration.  Beyond that, each integration approach has its own unique challenges that must be overcome to achieve targeted Vt and maintain Vt control.  In this work we will highlight those unique challenges and discuss what knobs can be used to achieve targeted Vts and maintain Vt control.

In FINFET gate last integration, dummy poly gate was formed first, and then high-k/metal gate stack is deposited after complete removal of the dummy gates.  In this integration, gate-fill and gate height are critical for Vt targeting and Vt control.  As gate CD become smaller, having void-free gate fill is a challenge.  A conventional CVD W-fill is shown to result in voids formation.  An alternative approach of W deposition is shown to improve fill and can also be used to modulate Vt.  In addition, gate height for FINFET gate last integration is defined by many processing steps.  Variation in any of the processing steps could translate into Vt variation.  Gate height variation reduction at key contributing steps is important to control the final gate height and ultimately, Vt variation.

In gate first integration, it is widely known that oxygen ingress prevention and gate encapsulation are critical for Vt control.  It has been reported that undesirable lateral oxygen diffusion is responsible for Vt instability [3].  A conformal, low temperature encapsulation is important to avoid oxygen ingress into the gatestack.  As transistor designs increase in complexity, this encapsulation layer must be conformal and not sensitive to wafer loading conditions.  Low temperature PEALD SiN gate encapsulation has been developed and shown to be superior to conventional CVD SiN[4].  In addition to these challenges, when integrating high-k gate first in FDSOI and as the SOI layer is thinned down to <15nm, special care must be taken to prevent the erosion of this thin channel.  Cleaning steps, oxide growth steps as well as annealing steps may consume or oxidize the already thin channel and need to be tailored to minimize further channel thinning.  Furthermore, an additional way to control Vt that is unique to FDSOI integration, namely the concept of back-biasing, will be discussed.


  1. C. Auth et al., VLSI Tech. Symp. Dig., p.131, 2012.
  2. N. Planes et al., VLSI Tech Symp. Dig., p.133, 2012.
  3. L. Brunet et al., VLSI Tech Symp. Dig., p.29, 2010.
  4. D.H. Triyoso et. al., Journal of Solid State Science and Tech., 2, p. N222, 2013.