Gate Metal

Monday, October 12, 2015: 15:00-16:00
105-B (Phoenix Convention Center)
Chair:
Marco Fanciulli
15:00
Best Paper Award
15:10
821
(Invited) Factors Impacting Threshold Voltage in Advanced CMOS Integration: Gate Last (FINFET) vs. Gate First (FDSOI)
D. Triyoso, R. Carter, J. Kluth, S. Luning, A. Child, J. Wahl, B. Mulfinger, K. Punchihewa, A. Kumar, L. Kang, R. Sporer, X. Chen, S. Straub, G. Bohra, S. Patil, X. Zhang, A. Chen, M. Togo (GLOBALFOUNDRIES), and R. Pal (GLOBALFOUNDRIES)
See more of: D04: Semiconductors, Dielectrics, and Metals for Nanoelectronics 13
See more of: Dielectric Science and Materials
<< Previous Session | Next Session >>