Optimized Novel Indium Antimonide Quantum Well Field Effect Transistor for High-Speed and Low Power Logic Applications

Monday, October 12, 2015: 09:10
105-B (Phoenix Convention Center)
R. Islam, M. M. Uddin (Chittagong University of Engineering & Technology), and M. A. Matin (Chittagong University of Engineering & Technology)
The physical gate length LG of the Si transistors are shrinking day by day to meet Moore’s law that states the number of transistors per integrated circuit doubles in every 24 months. It is projected that LG may be down to ~20 nm. Therefore, it is urgent need to be “energy efficient” which operates with the lowest switching power. Much effort has been paid to incorporate III-V nanoelectronics on the silicon platform due to highest intrinsic electron mobility. The InSb quantum well field effect transistor (QWFET) is a promising candidate for future high performance and low power logic applications [1,2]. In addition, recent success in depositing high-quality Al2O3 gate dielectrics by atomic layer deposition (ALD) on the InSb quantum wells (QWs) and completely depletion of the two-dimensional electron gas (2DEG) confined in InSb QW opens the prospects to fabricate high-quality InSb QW field effect transistor (FET) [3,4].

   An InSb QWFET with a 10 nm thick Al2O3 top gate insulator has been simulated by using quantum corrected Schrödinger-Poisson (QCSP) solution as shown in Fig. 1 (a). Gate voltage (Vg) dependent electron density (ns) and mobility (µ) is shown in Fig. 1 (b). A very high electron mobility 4.42 m2V-1s-1 at Vg= 0V is achieved which is at least ~180 times greater than that of Si NMOS. The confined 2DEG in InSb QW is completely depleted with a very small Vg= -0.25V (is called as the pinch–off voltage, Vp). The slope of the ns-Vg yields a giant gate controllability ratio of dns/dVg = ~ 5.2 × 1015m-2V-1 (estimated in the range of Vg=-0.2V to 0V). The room temperature conduction band (CB) and valance band (VB) profile of the proposed structure at Vg= 0 and -0.25V are calculated by QCSP as shown in Fig. 2. The QW is lifted above the Fermi level (EF) at Vg = -0.25V which is confirmed complete depletion (Vp) as shown in Fig. 1. Moreover, the hole accumulation prevents as the VB doesn’t touch the EF.  

The interface trap density (Dit) has been calculated using the equation Dit= -(dQit / (e × d(EF - EV))) where Qit is the net charge (difference between oxide and semiconductor charge) [4]. Energy dependent Dit and corresponding applied gate voltage (Vg) is shown in Fig. 3. Very low Dit is found to be 7.8 × 1014 – 3.7 × 1016 m-2eV- 1 at the interface between Al2O3 and Al0.1In0.9Sb top layer of the InSb QWFET, results a giant dns/dVg (Fig. 1b). It indicates that the EF is smoothly tuned by the Vg due to a very low Dit of the InSb QWFET. The capacitance-voltage (C-V) calculation has also been confirmed the low Dit and Vp of the proposed QWFET. The standard transistor characteristics with ID versus VDS at different Vg, transconductance (gm) have also been calculated and explained by the established theory and experimental explanation.

[1] T. Ashley et al. Proceedings 7th International Conference on Solid-State and Integrated Circuits Technology (SSICT), 2253 (2004).

[2] S. Datta, Microelectronic Engineering 84, 2133 (2007).

[3]  M. M. Uddin et al., Appl. Phys. Lett.101, 233503 (2012).

[4]  M. M. Uddin et al., Appl. Phys. Lett.103, 123502    (2013).

Fig. 1: (a) Cross section of InSb optimized QWFET layer structure with LG=100 nm and δ-doping (dashed line). (b) Electron density (ns) and mobility (μ) of the InSb QWFET as a function of gate bias (Vg) at 300 K. The dashed line points to the pinch-off voltage Vp

Fig. 2: Band profile (CB and VB) of the proposed InSb QWFET at 300 K. The Fermi level is shown at 0eV.  

Fig. 3: The interface trap density (Dit) as a function of EF-EV obtained from the QCSP solution with corresponding applied Vg (V).