Optimized Novel Indium Antimonide Quantum Well Field Effect Transistor for High-Speed and Low Power Logic Applications

The physical gate length L_G of the Si transistors are shrinking day by day to meet Moore’s law that states the number of transistors per integrated circuit doubles in every 24 months. It is projected that L_G may be down to ~20 nm. Therefore, it is urgent need to be “energy efficient” which operates with the lowest switching power. Much effort has been paid to incorporate III-V nanoelectronics on the silicon platform due to highest intrinsic electron mobility. The InSb quantum well field effect transistor (QWFET) is a promising candidate for future high performance and low power logic applications [1,2]. In addition, recent success in depositing high-quality Al₂O₃ gate dielectrics by atomic layer deposition (ALD) on the InSb quantum wells (QWs) and completely depletion of the two-dimensional electron gas (2DEG) confined in InSb QW opens the prospects to fabricate high-quality InSb QW field effect transistor (FET) [3,4].

   An InSb QWFET with a 10 nm thick Al₂O₃ top gate insulator has been simulated by using quantum corrected Schrödinger-Poisson (QCSP) solution as shown in Fig. 1 (a). Gate voltage (V_g) dependent electron density (n_s) and mobility (µ) is shown in Fig. 1 (b). A very high electron mobility 4.42 m²V^-1s^-1 at V_g= 0V is achieved which is at least ~180 times greater than that of Si NMOS. The confined 2DEG in InSb QW is completely depleted with a very small V_g= -0.25V (is called as the pinch–off voltage, V_p). The slope of the n_s-V_g yields a giant gate controllability ratio of dn_s/dV_g = ~ 5.2 × 10¹⁵m^-2V^-1 (estimated in the range of V_g=-0.2V to 0V). The room temperature conduction band (CB) and valance band (VB) profile of the proposed structure at V_g= 0 and -0.25V are calculated by QCSP as shown in Fig. 2. The QW is lifted above the Fermi level (E_F) at V_g = -0.25V which is confirmed complete depletion (V_p) as shown in Fig. 1. Moreover, the hole accumulation prevents as the VB doesn’t touch the E_F.  

The interface trap density (D_it) has been calculated using the equation D_it= -(dQ_it / (e × d(E_F - E_V))) where Q_it is the net charge (difference between oxide and semiconductor charge) [4]. Energy dependent D_it and corresponding applied gate voltage (V_g) is shown in Fig. 3. Very low D_it is found to be 7.8 × 10¹⁴ – 3.7 × 10¹⁶ m^-2eV^{- 1} at the interface between Al₂O₃ and Al_0.1In_0.9Sb top layer of the InSb QWFET, results a giant dn_s/dV_g (Fig. 1b). It indicates that the E_F is smoothly tuned by the V_g due to a very low D_it of the InSb QWFET. The capacitance-voltage (C-V) calculation has also been confirmed the low D_it and V_p of the proposed QWFET. The standard transistor characteristics with I_D versus V_DS at different V_g, transconductance (g_m) have also been calculated and explained by the established theory and experimental explanation.

[1] T. Ashley et al. Proceedings 7th International Conference on Solid-State and Integrated Circuits Technology (SSICT), 2253 (2004).

[2] S. Datta, Microelectronic Engineering 84, 2133 (2007).

[3]  M. M. Uddin et al., Appl. Phys. Lett.101, 233503 (2012).

[4]  M. M. Uddin et al., Appl. Phys. Lett.103, 123502    (2013).

Fig. 1: (a) Cross section of InSb optimized QWFET layer structure with L_G=100 nm and δ-doping (dashed line). (b) Electron density (n_s) and mobility (μ) of the InSb QWFET as a function of gate bias (V_g) at 300 K. The dashed line points to the pinch-off voltage V_p. 

Fig. 2: Band profile (CB and VB) of the proposed InSb QWFET at 300 K. The Fermi level is shown at 0eV.  

Fig. 3: The interface trap density (D_it) as a function of E_F-E_V obtained from the QCSP solution with corresponding applied V_g (V).