(Invited) MOS Interface Control Technologies for Advanced III-V/ Ge Devices

Monday, October 12, 2015: 10:30
105-B (Phoenix Convention Center)
S. Takagi (The University of Tokyo, JST-CREST), C. Y. Chang, M. Yokoyama (JST-CREST, The University of Tokyo), K. Nishi, R. Zhang (Zhejiang University, The University of Tokyo), M. Ke, J. H. Han (The University of Tokyo, JST-CREST), and M. Takenaka (The University of Tokyo, JST-CREST)
One of the most critical issues for III-V/Ge MOSFETs, which have been regarded as a promising CMOS structure under sub 10 nm regime, is formation of superior gate stacks satisfying the requirements of thin EOT, excellent MOS interface quality enabling high channel mobility and low S factor and high reliability. As a result, MOS interface control engineering is still of paramount importance. In this presentation, we focus on viable III-V/Ge gate stack technologies by using ALD high-k films for realizing these requirements.

Two types of III-V semiconductors, InGaAs- and GaSb-based materials, have currently stirred a strong interest for n- and p-MOSFETs, respectively. In addition, the GaSb-based materials have become important for tunnelling FET application. As for InGaAs gate stacks, the insertion of 0.2-nm-thick ultrathin Al2O3 inter-layer can effectively improve the HfO2/InGaAs interface properties, resulting in 1-nm-thick CET HfO2/Al2O3/InGaAs MOS gate stacks with low gate leakage of 2.4×10-2 A/cm2 [1]. The resent studies have revealed that ALD La2O3 gate stacks can yield lower Dit than the Al2O3 ones [2, 3], indicating that La2O3 can be a promising high k material for III-V gate stacks. On the other hand, we have found that the InGaAs gate stacks using La2O3 only can include a large amount of slow traps. We present that ultrathin La2O3 interface control layers combined with Al2O3 and HfO2 can optimize both fast interface state density and slow trap density near the MOS interfaces.

As for GaSb gate stacks, much higher Dit of Al2O3/GaSb MOS interfaces than that of Al2O3/InGaAs MOS interfaces severely degrades the device performance. Any thermal processing significantly is observed to increase Dit at Al2O3/GaSb interfaces [4]. It is shown that InAs passivation can effectively improve the MOS interface properties and the thermal stability [5]. As a result, 2.5-nm-thick InAs passivation can provide the peak hole mobility of 159 cm2/Vs for Al2O3/InAs/GaSb pMOSFETs [6]. In addition, surface treatment for InAs/GaSb hetero-structures by buffered HF, instead of conventional (NH4)2Sx, can further improve Dit at the MOS interfaces with Al2O3 [7].

As for Ge gate stacks, we have presented ultrathin EOT Al2O3/GeOx/Ge and HfO2/Al2O3/GeOx/Ge gate stacks, fabricated by a plasma post oxidation method [8, 9]. HfO2/Al2O3/GeOx/Ge gate stacks with EOT of 0.76 nm have yielded (100) Ge p- and n-MOSFETs with high peak mobility of 546 cm2/Vs and 690 cm2/Vs, respectively [9]. We evaluated limiting factors of electron and hole mobility in Ge n- and p-MOSFETs. In a high Ns region the Ge MOS channel mobility is significantly degraded by surface roughness scattering as well as trapping of free electrons and holes into interface states inside the conduction and valence bands [10, 11]. The mobility in the high Ns region can be improved by reduction in surface roughness through a layer-by-layer plasma oxidation process [10]. Also, atomic Deuterium annealing can reduce Dit inside the bands, resulting in higher effective mobility [12]. However, the decrease in slow trap density for the Ge MOS gate stacks is a strong concern. While we observed the decrease in slow trap density near the valence band edge of Ge for ALD AlYO3/GeOx/Ge gate stacks formed by plasms post oxidation [13], the reduction in slow trap density for n-MOSFETs has not been obtained yet. Further optimization of Ge gate stacks is strongly needed for obtaining sufficient reliability in Ge CMOS.

This work was partly supported by JST-CREST, the Grant in-Aid for Scientific Research through the MEXT (26249038), and the Innovation Research Project on Nano electronics Materials and Structures from NEDO. The authors would like to thank Drs. H. Yamada and O. Ichikawa in Sumitomo Chemical Corporation, and Drs. H. Yokoyama and M. Mitsuhara in NTT for their collaborations.

References [1] R. Suzuki et al., APL 100, 132906 (2012) [2] D. H. Zadeh et al., IEDM (2013) 36 [3] C.-Y. Chang et al., SISC (2014) 4.5 [4] M. Yokoyama et al., APL 104, 262901 (2014) [5] M. Yokoyama et al., APL 106, 122902 (2015); [6] M. Yokoyama et al., VLSI symp. (2014) 28 [7] K. Nishi et al., VLSI symp. (2015) [8] R. Zhang et al., APL 98, 112902 (2011) [9] R. Zhang et al., TED 60, 927 (2013) [10] R. Zhang et al., TED 61, 416 (2014) [11] R. Zhang et al., TED 61, 2316 (2014) [12] R. Zhang et al., VLSI symp. (2013) T26 [13] M. Ke et al., Microelectron. Eng. (2015)