Electroplated Cu Grids on Crystalline Silicon Solar Cells and Its Long Term Degradation

Tuesday, October 13, 2015: 16:00
Ellis West (Hyatt Regency)
Q. Huang (IBM TJ Watson Research Center)
Replacing screen printed Ag with electroplated Cu for silicon solar cell metallization is of great interest because of the high conductivity, low cost, and easy integration with laser patterning of the latter approach. The contact resistance and adhesion between Cu grid and Si emitter as well as the concern of Cu diffusion into the Si has motivated the invention of Silicide-Ni-Cu metallization.[1,2] In addition, the method of light induced plating or light assisted plating was invented decades ago and enabled the electroplating on the photoelectric device.[3-5] While this approach has been proposed for more than a decade, the details of the electroplating process for this new metallization scheme is not well understood. Furthermore, the impacts of this new metallization scheme on the long term stability of solar cells has not been studied until very recently.[6,7]

This paper will present the light assisted plating of Ni and the silicide formation on single crystalline silicon solar cells as well as the thermal degradation of the Cu metalized cells. Solar cells in real operation in the field will be challenged not only by heat, but also by moisture, radiation, and other natural stresses. While the reliability tests for Si solar cells with screen-printed Ag grid have been standardized already, the impacts of these stress elements are unknown to the Cu grids and are typically convoluted.

In this study, solar cells with Cu metallization were annealed at different elevated temperatures to speed up the degradation. Degradation behaviors of the grids after up to 3 years were studied. Different materials were also evaluated and compared for improvement in the grid reliability.  For example, figure 1 shows a comparison between the solar cells with the pure Ni layer and NiCo layer. The presence of Co apparently improved the stability of the final grids during the stress tests at elevated temperature. Further detailed discussion will be provided in the talk.


  1. D. A. Yates, US Patent 4,609,565 (1986).
  2. K. Holdermann, US patent 5,543,333 (1996).
  3. L. F. Durkee,  Patent No. 4144139 (1979).
  4. L. A. Grenon, US patent 4,251,327 (1981).
  5. G. Hamm and D. L. Jacques,  Patent No. 7955977 (2011).
  6. J Bartsch, A Mondon, K Bayer, C Schetter, M Horteis, and S W Glunz, J. Electrochem. Soc., 157, H942 (2010).
  7. J Bartsch, A Mondon, C Schetter, M Horteis, S W Glunz, IEEE 35th PVSC, Honolulu HI (2010).