Set and Reset Voltage Interdependence in Resistive Switching Memory Cells

Thursday, October 15, 2015: 15:30
Curtis B (Hyatt Regency)
G. Ghosh (ECE Department Virginia Tech) and M. K. Orlowski (ECE Department Virginia Tech)
Resistive switching (RS) devices are a primary candidate to supplant current NVM memory based on floating gate MOSFET. However, RS devices suffer from broad distributions of set and reset threshold voltages.  The state transition from the initial high resistance state (HRS) to a low resistance state (HRS) is called SET process characterized by a critical voltage Vset.  A high current passing through the filament can rupture the bridge and restore the HRS state, in a so-called RESET process of the device and characterized by a critical voltage Vreset. Cu/TaOx/Pt memory cells have been fabricated with 16 nm thick oxygen-deficient TaOx formed by e-beam evaporation. The bottom Pt electrode has been deposited by evaporation and patterned by lift-off on a thermally oxidized Si wafer. The top Cu electrode lines were processed in the same way but patterned perpendicularly to the bottom Pt lines. The width of the metal lines varies between 1μm and 35μm. When a positive voltage is applied to the active electrode, Cu cations dissolve in the solid electrolyte and migrate through it. Cu cations are electrochemically reduced on the Pt cathode. As more Cu atoms accumulate, a nanoscale metalic filament (CF) forms at Vset a conductive path between two electrodes. Here, we report a statistical dependence of set voltage, Vset, on the preceding reset voltage, Vreset, for the same device. Such (Vset, Vreset) pairs have been collected for a multitude of devices in resistive RRAM Cu/TaOx/Pt memory arrays. This dependence appears to be linear and is explained in terms of two interlocking mechanisms responsible for the formation and dissolution of the filaments. The Vset~Vreset dependence on a multitude of memory cells can be replicated also on a single device by intentionally varying Vreset values by the application of different linear voltage ramp rates (rr). The latter mechanism is well modeled under the assumption that a critical heat Qcrit deposited locally in the filament triggers the rupturing of the Cu conductive filament.  Qcrit can be obtained as a time integral over the instantaneous power p(t)=(rr·t)2/Ron from t=0 till the reset time treset=Vreset/rr. The experimental Vreset data shows a cubic root dependence on the voltage ramp rate in close agreement with the model, i.e. |Vreset|=Vreset,min +γ(rr)1/3. The model predicts also that γ=(3·Qcrit·Ron)1/3, with Ron being the resistance of the on-state and is fully borne out by experiment on several different Ron values. Ron can be controlled by the compliance current Icc during the set operation according to Ron=0.17/Icc.  Moreover, from experimental data and model assumptions, we can extract Qcrit to amount to 6μJ per erase operation. A separate mechanism is proposed to explain the impact of Vreset value on the subsequent Vset value, in terms of increased Cu+ ion mobility at high local temperatures just after the reset and the time τdiss needed to dissipate the Qcrit heat. A higher |Vreset| translates then into larger rupturing gap Δ than a low |Vreset| according to Δ=(|Vreset|/Δo)·μCu+·τdiss where Δo is the initial ruptured gap due to high temperature at the most resistive segment of CF caused by Joules heating. Larger rupturing gate translates then to larger Vset~Δ.  The Vreset~Vset relation can be used to tighten Vset and Vreset distributions. RRAM suffers from broad natural distributions of Vset and Vreset obtained at fixed ramp rates. In our method, an array of memory cells with large spread of initial Vset values, has been subjected to three different ramp rates:  the devices with high Vset have been reset at a lower ramp rate than devices with low Vset values. The moderate Vset values have been subjected to intermediate ramp rate. The effect of such pre-conditioning results in much tighter distribution of Vreset. The subsequent set operation at constant ramp rate leads to a very tight distribution of Vset. Repeated set and reset operations converge on a very tight Vset and Vreset distributions. This means that the conditioning step has to be applied only once. A natural broad distribution has been selected with experimental data consisting essentially of three clusters of Vset values: (i) centered on Vset=1.0V, (ii) centered on Vset=3.8V, and (iii) data lying in-between. For the natural distribution, the mean value and standard deviation are Vset,m=2.5V and σ=1.35V, respectively. The devices of cluster (i) underwent a reset operation at ramp rate 1V/s, the devices of cluster (ii) at a ramp rate of 1mV/s, while devices with natural Vset in-between have been reset at 10mV/s. After this very simple and not further optimized procedure, a very tight (10x tighter) distribution has been obtained with Vset,m=2.13V and σ=0.14V.