(Invited) Integration Challenges of Ferroelectric Hafnium Oxide Based Embedded Memory

Wednesday, October 14, 2015: 14:40
Curtis B (Hyatt Regency)
J. Müller, P. Polakowski, J. Paul, S. Riedel, R. Hoffmann (Fraunhofer IPMS-CNT), M. Drescher (Fraunhofer IPMS-CNT), S. Slesazeck (NaMLab gGmbH), S. Müller, H. Mulaosmanovic (NaMLab), U. Schröder (NaMLab gGmbH), T. Mikolajick (NaMLab gGmbH), S. Flachowsky, E. Erben, E. Smith, R. Binder, D. Triyoso, J. Metzger (GLOBALFOUNDRIES), and S. Kolodinski (GLOBALFOUNDRIES)
System on chip (SoC) embedded memory solutions promise small form factors and high operating speed, as well as a high energy and cost efficiency. Single cell scalability and basic memory parameters such as data retention, cycling endurance and disturb characteristics on array level are important aspects in stand-alone memory development and can serve as a guideline for embedded solutions. However, one of the key aspects in embedded memory development is compatibility of the memory technology to its underlying complementary metal oxide semiconductor (CMOS) platform. This includes the voltage requirements for logic and memory operation, the need for additional lithographic steps and minimally CMOS invasive integration efforts, as well as the introduction of new materials and related contamination concerns. Especially in state of the art high-k metal gate (HKMG) CMOS technologies at minimum feature size (F) these aspects proof rather challenging when searching for a suitable embedded memory solution. As a consequence most approaches result in large memory cells of multiple F2 or leave a BEoL integration of the memory cell as the only viable option.

With the introduction of ferroelectric hafnium oxide, however, a scalable one-transistor (1T) memory solution derived from the conventional HKMG transistor was presented for the 2X nm node. The therewith close resemblance of the memory and logic transistor appears ideally suited for combining nonvolatile data storage and logic circuitry on the same chip. Nevertheless, in order to fulfill these expectations and to ease manufacturing issues this resemblance has to be as close as possible. In the context of a minimally invasive memory integration strategy this means that ideally the ferroelectric hafnium oxide based memory transistor has to adapt to the HKMG transistor in terms of thermal budget and post treatments, vertical and lateral dimensions, the use of stress engineering, as well as metal gate and work function engineering. Based on experimental gate first transistor and metal insulator metal (MIM) capacitor data these aspects together with embedded memory requirements will be analyzed and critically discussed.