Rapid thermal annealing (RTA) enabled shallow junction formation requires very short time annealing at high temperatures for low thermal budget. RTA is typically done by lamp-based radiant heating. Radiant power from lamp arrays is close-loop controlled to execute the temperature of the Si wafer as programmed. The increase of annealing temperature and the decrease of annealing time are generally required for more aggressive device scaling. However, the use of non-equilibrium radiant heat sources (photon energy from lamp arrays) makes the heating process sensitive to the optical properties of the Si wafers.

Local temperature non-uniformity during RTA is considered an important contributor for within-die process variations which cause significant problems for advanced complimentary metal-oxide-semiconductor (CMOS) device manufacturing. RTA-induced variations strongly depend on circuit layout patterns and optical properties of exposed materials on the surface of the Si wafers. This phenomenon is often referred to as “pattern effect” known from the early days of RTA introduction in the semiconductor industry.

In efforts to reduce the “pattern effect”, various approaches have been proposed and implemented in device manufacturing. Shielding device patterns from the radiant heat source is a common approach, having limited success. It is done by either placing a dummy wafer on the pattern side of the Si wafer or backside heating. One other common approach is to homogenize the optical properties of the pattern side of Si wafer by either adding an optical absorption layer or dummy patterns. A differential thermal energy control technique is also proposed for pattern effect suppression. Non-radiative heating techniques have been proposed and demonstrated effectiveness of this “pattern effect” suppression.    

In this paper, various silicide contact formations on implanted single crystalline Si in source/drain region and implanted poly-Si in gate region were studied over wide ranges of RTA temperature and time using a hot wall RTA system which uses mainly natural convection and conduction through ambient gas. Dopant profiles of the silicide and doped Si after silicidation in the hot wall RTA system were characterized. Proposed possible silicide formation and dopant diffusion mechanisms are discussed. Differences between radiant heating and non-radiant heating on the silicide formation and dopant profiles are compared. The pattern and emissivity insensitive dopant activation and silicide contact formation annealing results will be introduced and potential applications of the hot wall RTA technique in advanced CMOS devices will be proposed.