The emerging 3-dimensional integration relies on components such as through-silicon vias (TSVs) and micro-bumps for vertical stacking [1, 2].  In a typical micro-bump fabrication process, a thin Cu seed layer is coated with a thick layer of photoresist. After exposure and development, cylindrical openings are formed in the photoresist layer.  Depending on the application, bumps with single or multiple metal layers, one of them typically being Cu, are deposited. The removal of photoresist is followed by wet etch of the Cu seed, revealing individual micro-bumps.  While Cu in the ‘body’ of the micro-bump is deposited electrochemically, the Cu seed layer is typically fabricated using physical vapor deposition (PVD).  As the plated Cu etches up to 30% faster than PVD Cu [3], the Cu part of the bumps may suffer from significant radial etch before the seed is removed completely. Figure 1 shows the post-etch SEM image of a micro-bump with Cu-Ni-Sn metal stack. For 4 µm micro-bumps plated on a 200 nm Cu seed, the contact area with the pad will be reduced by about 25 % after seed etch. In order to minimize the ‘under-etch’ of the micro-bumps, the thickness of the Cu seed layer should be reduced.  However, the reduction of Cu seed layer thickness leads to the well-known ‘terminal effect’ on the wafer scale [4]. Figure 2 illustrates the cross-section of a plating cell. Due to the potential drop along the radial direction, the plating current density decreases from the wafer edge to the wafer center, resulting in the micro-bump height decreasing from the wafer edge to the wafer center. 

In this study a quick and cost-effective approach was developed to evaluate the micro-bump height uniformity on wafer level.  We studied dependency of micro-bump height uniformity on Cu seed thickness using 300 mm wafers and demonstrated the impact of terminal effect on height variation along the radial direction. By using only the experimentally measured i-ηcurve for the kinetics, numerical simulation of the wafer-scale plating uniformity was significantly simplified. As the proposed methodology required no explicit knowledge of the plating bath composition and only involved coupon-scale experiments, it provided a fast and cost-effective way to evaluate the effectiveness of proprietary plating chemistries with respect to wafer-scale height uniformity of micro-bumps. The usefulness of the proposed approach was supported by the good match between simulation results and the corresponding experimental measurement. Although the simulation capability was only demonstrated for Cu, the same approach can be applied to other layers deposited for micro-bumps. The overall uniformity can be readily calculated through summation of all the layers involved. The simulation program can also be modified to address different profile control approaches such as additional current collectors or anodes with modified geometry.

References:

[1] Y. Civale, D. S. Tazcan, H. G. G. Philipsen, P. Jaenen, R. Agarwal, F. Duval, P. Soussan, Y. Travely, E. Beyne, Die stacking using 3D-wafer level packaging copper/polymer through-Si via technology and Cu/Sn interconnect bumping,” IEEE International 3D System Integration Conference, 2009.

[2] R. Agarwal, W. Zhang, P. Limaye, R. Labie, B. Dimcic, A. Phommahaxay, P. Soussan, Cu/Sn microbumps interconnect for 3D TSV chip stacking, IEEE Electronic Components and Technology Conference (ECTC), 858 (2010).

[3] Wet etch rate PVD Cu vs ECD Cu is internal imec data for a given specific process.

[4] S. Armini, P.M. Vereecken, Impact of terminal effect on Cu plating: theory and experimental evidence, ECS Transactions 25 (2010) 185.