One of the key active manufacturing technologies for 3D integration is through silicon vias (TSVs), which involves etching of deep vias in a silicon substrate that are filled with an electrodeposited metal, and subsequent removal of excess metal by chemical mechanical planarization (CMP). Electrodeposition often results in undesired voids in the TSV metal fill as well as a thick overburden layer [[i],[ii]]. These via plating defects can severely degrade interconnect properties and lead to variation in via resistance, electrically open vias, and trapped plating chemicals that present a reliability hazard. Thick overburden layers result in lengthy and expensive CMP processing.

We have recently developed a contactless technique that pursues a viable method of depositing a high quality metal inside vias with true bottom-up filling, using an additive-free deposition solution [[iii]]. The mechanism is based on a novel concept of electrochemical oxidation of backside silicon that releases electrons, and subsequent chemical etching of silicon dioxide for regeneration of the surface. The set-up consists of a reactor with two chambers. A silicon wafer with vias is placed and sealed between the two chambers. The front side of the wafer—the via side—is in contact with a deposition solution with an anode immersed in the bath. The backside of the wafer is in contact with an etchant solution (HF) with an immersed Pt mesh or graphite cathode. Silicon in contact with the etchant solution undergoes two-step dissolution, the first being electrochemical oxidation to SiO₂ (see reaction R1) and the second involving chemical etching of SiO₂(see reaction R2).

Si + 2H₂O = SiO₂ + H₂ + 2H⁺ + 2e^-                                                                                              (R1)

SiO₂ + 6HF= H₂SiF₆ + 2H₂O                                                                                                          (R2)

The electrons at the silicon/etchant solution interface resulting from first reaction are conducted through the bulk of silicon wafer to be consumed at the interface between the bottom of vias and the deposition solution. At this later interface, metal ions are reduced and deposited on the via bottom ensuring a bottom-up fill process. This prevents the formation of voids or seams because the driving force for the reaction is provided through the wafer rather than along a seed layer on the surface of the sample, as is typically the case in a traditional electro-deposition process.

A comprehensive process model has been developed to analyze the kinetics and the mechanism of the deposition process and to uncover the role of different controlling steps.  The model is used in the analysis of experimental data with the goal of selecting and optimizing the operational parameters to achieve high-quality fills with desired deposition rates.   The process model includes the key aspects of the fluid mechanics, mass transfer, chemical reactions, and surface interactions/deposition occurring simultaneously in the process.