As the Back - End - of - Line (BEOL) Interconnects are scaling down to nanometer regime with multiple levels of metallization , need for ultra thin diffusion barrier layers arise. Self assembled monolayer (SAM) is an ideal solution to satisfy the requirement of an ultra thin barrier layer to avoid Copper difussion. However, wet chemical processes are preferably avoided in Complimentary - Metal - Oxide - Semiconductor (CMOS) fabrication process. Accordingly , a novel technique to form SAM of Zinc (||) tetraphenyl hydroxy porphyrin (ZnTPPOH) in vapor phase on Inter - Layer Dielectric (ILD) materials is developed in present work to suit the industry process flow and be integreable in CMOS fabrication. The vapor phase SAM formation of ZnTPPOH is investigated employing different techniques and studies from simple contact angle measurements, spectroscopic measurements such as x-ray photoelectron spectroscopy (XPS) , fourier transform infrared spectroscopy (FTIR) , Ultra Violet - Visible Spectroscopy (UV - Vis) , and the atomic force microscopy (AFM) , etc. The vapor phase SAM of ZnTPPOH was formed on different ILD materials such as Black Diamond , Hydrogen silsesquioxane , etc and also on Silicon dioxide substrates. Selective formation of SAM in vapor phase was studied using different substrates such as Gold , Copper , etc .

The vapor phase SAM was incorporated in Metal - Oxide - Semiconductor  Capacitor (MOSCAP) structure. Copper was used as metal and the Vapor phase SAM was formed on Oxide / ILD materials so as to sandwich between the Copper and ILD, to repel and isolate the Copper in order to avoid any diffusion of Copper into the ILD materials. Capacitance - Voltage (CV) measurements , Current - Voltage characterization were done under bias and temperature stress  on the MOSCAP devices to investigate the electrical performance of MOSCAP device and efficiency of ZnTPPOH vapor phase SAM as a barrier layer. Similarly blanket MOSCAP stack was formed and subjected to temperature stress and the extent of copper diffusion was investigated using (SIMS). Scanning electron microscopy (SEM) and scotch tape tests were done to observe improvement in adhesion of Copper to the ILD materials.

The vapor phase SAM process was optimized and devloped to suit the CMOS technology and demonstrated as an effective copper diffusion barrier layer for interconnects. This technique opens up a whole new set of opportunities to scale down the barrier layer thickness. Integrating such bottom-up approach within the CMOS fabrication process would make scaling to 7nm and beyond possible where interface layers, dielectrics, and semiconductor films will be on a molecular level.