Over the past decades, aggressive and continuous transistor scaling according to Moore’s law has provided ever increasing device performance and density. For advanced (sub-)5nm nodes, to keep the growth pace, several options can be considered in terms of material choices, device architectures and circuits design. However, further cells scaling using conventional 2D layouts is becoming more and more challenged by key factors such as the physical limits on gate and contact placement and interconnect routing congestion. Vertical nanowire (VNW) devices appear particularly well placed to overcome some of these limitations, but require early process-design cross-disciplinary interactions to address the technological and design challenges/opportunities of moving from a 2D to a 3D layout configuration for CMOS. In this work, we will address some of these aspects, focusing first on a comparative analysis review of performance, parasitics and layout efficiency between VNWFETs (3D layout) and lateral nanowire (LNW) FETs or finFETs (2D layout), followed by a comprehensive overview of some key integration aspects regarding VNWFET devices fabrication.

In VNWFETs, since the gate length (L_gate) is defined vertically, it can be relaxed without area penalty, which in turn also allows some relaxation in the NW diameter, while keeping optimum short-channel-effects control. This is an important advantage of the vertical device architecture as several theoretical studies predict mobility degradation below a certain NW dimension, which would also cancel off the gains of using high-mobility channels such as Ge or III-V over silicon [1,2]. Moreover, L_gate relaxation is an important knob for variability optimization and leakage control, critical in scaled SRAMs. In terms of layout, VNWFETs can enable more compact cells [2,3], for instance by placing two pull-up transistors on the same row of a SRAM cell, saving around 30% area in comparison to a finFET-based SRAM [2]. A comparative simulation analysis in [4] of NAND library cells also suggests promising speed gains and power consumption reduction when switching from a 7nm Si-baseline finFET technology to 5nm Si VNWFETs. In addition, despite their potential for lower parasitic RC, VNWFETs asymmetry for source/drain wiring needs to be taken into account in circuit design and in processing for bottom access resistance optimization [2,5].

From an integration perspective, two main routes can be considered for device fabrication: channel-first or channel-last. In this work, we will focus on the first approach for added flexibility in terms of channel material choice [Si, (Si)Ge, III-V] and also control of the channel (defects) quality. Channel body (NW pillar) definition is done using 193nm immersion lithography followed by dry-etch. For the particular case of III-V, a bottom-up approach can also be considered for the NWs growth [6] (Fig.1). NW diameter (CD) shrinkage by dry-etch is challenged by the local CD uniformity control of the pillars within the NW arrays and their high aspect-ratio. Further CD reduction, and potentially also smoothening of the NW sidewalls, can be obtained by applying n cycles of low-temperature, [O₃-oxidation -> oxide etch] for Si-based pillars, digital etch for III-V pillars [7]. With regards to Si NW doping, for simplicity in terms of junction formation, we rely on growing up to three stacked layers of (uniformly doped) Si epi. A wide doping range for a given layer and a sharp doping concentration steepness between doped regions are feasible via tuning of the growth conditions such as pressure and B₂H₆ flow (for B-doped Si epi, PMOS). For extra simplicity, junctionless type of devices can also be particularly interesting to consider as they do not require junctions [8]. In a vertical device flow, control of the thickness of the different layers surrounding the NW pillars is key (Fig.2), both for a gate-first or a gate-last scheme, the latter enabling further options for device fabrication such as decoupling the gate module from doping/series resistance optimization for the top part of the NW. Here, layout dependences observed for several dry and wet etch processes and specific etch-back challenges (e.g., W surface roughness control) triggered the need for introduction of alternative schemes for improved process control of the layers on the wafers.

References

[1] K. J. Kuhn, IEEE Trans. Elect. Dev., 59(7), p.1813 (2012);

[2] A. V.-Y. Thean et al., VLSI Tech. Dig., p.26 (2015);

[3] H. Na et al., IMW Tech. Dig., p.1 (2011);

[4] V. Moroz et al., IEDM Tech. Dig., p.180 (2014);

[5] S. Maheshwaram et al., IEEE Trans. Elect. Dev., 60(9), p.2943 (2013);

[6] K. Tomioka et al., IEDM Tech. Dig., p.88 (2013);

[7] X. Zhao et al., IEDM Tech. Dig., p.695 (2013);

[8] A. Veloso et al., VLSI Tech. Dig., p.138 (2015).