(Invited) Evaluation of Stacked Nanowires Transistors for CMOS: Performance and Technology Opportunities
L. Gaben (STMicroelectronics, Crolles, France, CEA-LETI MINATEC Campus), S. Barraud (CEA-LETI MINATEC Campus), M. P. Samson (STMicroelectronics, Crolles, France), M. A. Jaud, S. Martinie, O. Rozeau, J. Lacord (CEA-LETI MINATEC Campus), C. Arvet (STMicroelectronics, Crolles, France), C. Vizioz (CEA-LETI MINATEC Campus), J. Bustos (STMicroelectronics, Crolles, France), J. A. Dallery (VISTEC ELECTRON BEAM GmbH), S. Pauliac, V. Balan, C. Euvrard-Colnat, C. Perrot, V. Loup (CEA-LETI MINATEC Campus), P. Besson (Univ. Grenoble Alpes), J. M. Hartmann (Univ. Grenoble Alpes, CEA-LETI, MINATEC Campus), S. Monfray, F. Boeuf, T. Skotnicki (STMicroelectronics), F. Balestra (Grenoble INP-Minatec/CNRS), and M. Vinet (CEA-LETI MINATEC Campus)