Currently, nanowire (NW) transistors have been proven to be excellent candidates for advanced technology nodes. Specifically, electrostatic control is improved over FinFET for better performance and energy savings. Over the last ten years, many developments on nanowire fabrication and nanowire FETs have been proposed [2] [3] [4] [5]. Today, stacking several nanowires at such scale paves the way for a significant increase in the effective width and current density along with substantial savings in device footprint.
Stacked nanowires can be implemented with different geometries such as circular or square cross-sections. However, we recently confirmed [5] among other studies [6] that thin and wide devices, also labelled as nanosheets, provide the best performances with respect to the FinFET technology.
A further attractive aspect for the use of nanowires in transistors, is that it may be possible to keep some of the flexibility from the planar technologies. In contrast, FinFET technology imposes a discrete partitioning of the active area. In order to increase the output current of a given FinFET based gate, it may be necessary to add another fin to increase the footprint by one fin pitch. Using nanosheets transistors, channel width can be tuned to obtain the required amount of current with limited impact on footprint as discussed in [7].
Stacked nanowire technology is also appealing as one possible solution due to the fact that their integration can be derived from FinFET. Several groups are currently working on their integration trying to minimize the variations from FinFET Gate-Last process [8]. Two options were identified and labelled as NW first and NW last referring to the fabrication of the NW stack. In the former, several successive epitaxies are performed and patterned to form the active zone as a vertical fin, after which silicon or silicon germanium needs to be removed in order to leave suspended silicon or silicon germanium channels. In the NW last integration, selective removal of silicon germanium happens in between the spacers after the removal of the sacrificial gate. In this case, an etch stop layer must be created to prevent the final gate penetrating under the spacers. This etch stop layer must also be low K in order to recreate the missing spacer material in between the NWs. Due to this requirement, an alternative integration has also been investigated. In the NW first option the selective removal of silicon germanium is done before the first spacer patterning and deposition. This method is also coupled with the use of a hydrogen silsesquioxane (HSQ) resist. This flowable oxide can be exposed through the silicon nanowires and the remaining material left after developing can be used as a sacrificial gate during the gate last process. The spacer deposited afterward is able to wrap around the NWs and the oxide temporary gate. As a consequence, this method provides self-aligned gate and spacer.
In recent years, we have also come to focus on carrier transport in NW devices. We have produced several NW-FETs in trigate and Ω-gate shapes on SOI in which we measured electron and hole mobility. Face related transport was observed and improved by using proper strain engineering. Strained SOI and silicon germanium raised source and drain were found to have a significant impact on mobility [4]. Currently, this work is also being integrated in order to boost the performances of our stacked NW-FETs.
In this paper we propose a review of the NW architecture and of different integration concepts. Several key points for the performance optimization will be pointed out.
[1] Natarajan, S. et al. IEDM, 2014
[2] Ernst, T. et al. IEDM 2006
[3] Coquand, R. et al. VLSI 2013
[4] Barraud, S. et al. VLSI 2013
[5] Gaben, L. et al. SSDM 2015.
[6] Kim, Seong-Dong et al. S3S 2015
[7] Lacord, J. et al. SSDM 2012.
[8] Lauer, I. et al. VLSI 2015