In current the semiconductor technology, dielectric layers (SiO₂, high-k, low-k) are playing an increasingly crucial role in affecting the final performances, variability and reliability of CMOS and beyond CMOS (Ge, III-V) electron devices. In addition, dielectric materials have become the active layers (i.e. where the electron transport occurs) of novel memory device like Resistive-RAM (RRAM).

In this scenario, a full understanding of the dielectric material implications at device levels is required to connect the microscopic/atomic properties of the dielectric material to the macroscopic electrical characteristics of the device. In particular, the role of electrically active defects, originated by atomic level imperfections (e.g. atom vacancies in the lattice, grain boundaries, ions) and responsible for charge trapping, is crucial to understand the electrical performances, variability and reliability of electron devices, especially in nano-scaled devices.

To this purpose, we presented in this paper a novel simulation-based methodology that can be used for device/technology development to either interpret the electrical measurements (to extract defect/material characteristics and to design novel device concepts leveraging on defect engineering.

This methodology is based on a modeling and simulation environment that relies on a comprehensive multi-scaled physics-based description of the physical mechanisms governing the charge-transport and degradation inside dielectric stacks, including the associated power dissipation, temperature increase, ion/vacancy defect generation, and ion/vacancy diffusion and recombination. Physical parameters accounting for charge transport and defect diffusion/creation/recombination are calculated using ab-initio methods, i.e. DFT and molecular dynamics. Static electrical curves (I-V, C-V, G-V, BTI, charge-pumping, gate/drain current noise) as well as the material modification occurring during electrical stresses are reproduced in a Monte Carlo fashion that accounts for the device statistics.

This methodology is applied to investigate dielectric layers and defect properties of MOS transistors and passive devices.

A variety of electrical characteristics, i.e. I-V, C-V, G-V, I-V, dielectric relaxation, BTI, were considered to profile defects in the stacks of either conventional Si and beyond-Si (i.e. Ge and III-V) MOSFETs. Cross-correlating among different measurements allows extending the regions within the stack bandgap where defects can be profiled. Results allow identifying atomic nature of defects, and have been used for scaling and reliability prediction.

The same methodology was applied to investigate emerging memory devices, such as STO DRAM capacitors and HfO_x-based RRAM. The simulation of C-V, I-V and dielectric relaxation curves were used to extract defect properties in STO material, which are then used to investigate scaling potential of this material for DRAM application, given the strong constraints in terms of leakage current, surface capacitance and physical oxide thickness limitations.

Finally, simulations were used to check how O vacancy defects are exploited to engineer RRAM device operation (i.e. from forming to set/reset) and reliability.