The major reliability issue of metal-oxide-semiconductor field-effect-transistor (MOSFET) had been mainly hot carrier injection (HCI) until the late 1990s. However, negative bias temperature instability (NBTI) has been focused on since late 1990s until now because both aggressive scaling-down of gate oxide thickness and nitrogen incorporation into gate oxide, which mitigate HCI, enhance NBTI severely [1-2].

 Although the phenomenon of bias temperature instability (BTI) has been known for several decades, there is still no clear explanation regarding the roles of gate oxide thickness on NBTI degradation of p-MOSFETs. For example, N. Kimizuka et al. reported that NBTI lifetime in p-MOSFET with thin gate oxide is larger than that with thick gate oxide under equivalent oxide field stress in the range of 2.0 ~ 4.0 nm oxide thickness [3]. On the contrary, S. Mahapatra et al. reported that BTI could be enhanced in p-MOSFET with thinner gate oxide due to high diffusivity of H₂ in gate poly [4]. Meanwhile, G. Pobegen et al. reported that NBTI were all the same in p-MOSFETs with gate oxide thickness of 5.6, 13.9 and 29.1 nm [5].

 In this work, we tried to resolve conflicting experimental results reported in the literature: Since the reduction of gate oxide thickness will enhance electric field across gate oxide, the application of thinner gate oxide will deteriorate NBTI degradation such like threshold voltage shift (ΔV_t) caused by charge generation. However, it also increases oxide capacitance, reducing the effect of generated positive charge which is one of the main sources for NBTI degradation.

 We fabricated p-MOSFET devices with SiON gate oxide and p+ poly-silicon gate stack in the commercial graded production line through conventional DRAM full processes. We evaluated p-MOSFETs with two different thicknesses of gate oxide: One is p-MOSFETs with thin gate oxide of 3.36 nm (‘thin PMOS’ hereafter), and the other is p-MOSFETs with gate oxide of 7.27 nm (‘thick PMOS’ hereafter). We evaluated NBTI degradation electrically by measuring the threshold voltage (V_t) before and after NBT stress for 1,000 seconds at 125 °C with Agilent 4156C. By means of stressing for 1,000 seconds without a break and by measuring just after stress, we could minimize undesirable variations caused by recovery.

 Data shown in Fig. 1(a) represent ΔV_t caused by NBT stress of various gate voltages. In Fig. 1(a), the slope of ΔV_t for thin PMOS devices is steeper than that of thick PMOS. However, if we redraw the same data of ΔV_t as a function of oxide electric field (E_ox), then we have the same ΔV_tslope for both thin and thick PMOS devices regardless of gate oxide thickness, as shown in Fig. 1(b).

 NBTI has been known to be exponentially increased with oxide electric field [6], which expressed empirically as Eq. (1). Our NBTI data of both thin and thick PMOS have the identical B value of 0.69 cm/MV. Also, NBTI is generally known to be caused by both interface trap and positive oxide charge which were generated during the NBT stress [6]. The generated charges contribute to threshold voltage shift via Eq. (2).  Therefore, the total increased charge density (ΔN_total) can be written as Eq. (3).

 By using Eq. (3), the correlation between the increased trap density and the oxide field applied during the NBT stress test can be obtained from the data in Fig. 1(b), and the result is shown in Fig. 1(c), in which all data lay on the one straight line. This suggests that NBT stress with the equivalent oxide field causes the same amount of increased charges independent of gate oxide thickness. Therefore, Eq. (1) must be normalized by C_oxto count this observation as Eq. (4).

 As shown in Fig. 2, it is remarkable that NBTI degradation becomes the minimum at the condition of Eq. (5). NBTI drops drastically down to the minimum point and then rises with the increase of gate oxide thickness, which accounts for the previous conflicting experimental results.

 In summary, we found that the total increased charge density of the devices subjected to NBT stress is same as long as the equivalent electric field is applied, regardless of gate oxide thickness. By modifying the empirical equation for ΔV_t, we suggest that the optimal value of T_ox can be selected for a given gate voltage and oxide field acceleration coefficient. This finding can be served as the new guideline on selecting gate voltage and gate oxide thickness to minimize the NBTI degradation both for process development and integrated circuit design.