Driven by fabrication cost reduction and device performance improvement, the Silicon semiconductor  industry continues its never-ending pursuit of new approaches for fabricating integrated circuits. In this context, the monolithic integration of III-V semiconductors epitaxially grown on Si substrate have been attracting much attention as building blocks for next-generation electronics and photonics due to their potential intrinsic properties.

Direct heteroepitaxy of III-V compound semiconductors on Si has traditionally represented a formidable challenge, due to the high material mismatch (lattice parameter, polarity, thermal coefficient, ...) between Si and III-V semiconductors generating high density of defect density during the epitaxial process. To overcome this, selective area growth of III-Vs in a pre-patterned Si substrate by Selective Area Metal-Organic Vapor Phase Epitaxy allow the possibility to obtain high quality and reduced defect density III-V based active layers onto standard Si(001) substrate.

 Using this approach we integrate III-V materials monolithically on Si while focusing on both ultimate trench widths (W < 20 nm) scaling as well as relaxed trench dimension in function of the targeted application. We report here on the heteroepitaxy of InP buffer on initiated from a <111> V-groove Si surface and discuss the unique relaxation mechanism of such compound with respect to Si substrate. We derived a fundamental understanding and theoretical modeling of the growth mechanisms in STI trenches as well as the determining role of the InP nucleation layer. The subsequent growth approach of InGaAs active layer, used for both nFET or Laser applications, is further studied.

Finally, III-V based electronic and photonic devices realized using selective area growth technique are presented and benchmarked to the current state of the art.