The miniaturization of traditional planar Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) becomes quite challenging for very short channel devices as the formation of ultra-sharp source and drain junctions with a high process complexity is needed [1]. Junctionless Field Effect Transistors (JLFETs) are considered promising for the sub-20 nm era due to their constant doping profile from source to drain [2]. Compared to the conventional MOSFETs, they provide a great scalability without the need for rigorously controlled doping and activation techniques as well as reduced Short Channel Effects (SCEs) – like subthreshold slope degradation, threshold voltage roll-off and drain-induced barrier lowering (DIBL) [3]. Among JLFET families, Cylindrical Gate-All-Around JLFET (CGAA JLFET) possesses superior short channel controllability and has therefore attracted considerable attention from the researchers [4]. A number of studies based on the analytical solutions have been performed to anticipate the performance of CGAA JLFET in the subthreshold region [5-7]. But all of them only put a focus on two-dimensional (2D) electrostatic potential model in the channel region which is further used to determine DIBL and Subthreshold Swing (SS) numerically. However, a simple and complete analytical treatment for SS is necessary not only to improve the short channel performance of CGAA JLFET but also to provide basic designing guidance for CGAA JLFET. In this work, we propose a physically based analytical model of SS for CGAA JLFET and make a comparative study of short channel behavior with the variation of different physical parameters such as, oxide thickness, channel diameter, gate electrode etc.

The schematic cross-sectional view of an n-channel CGAA JLFET considered in this work is shown in figure 1. Due to the existence of cylindrical symmetry in the structure, we have employed a cylindrical coordinate system z-axis and r-axis which are parallel and vertical to the channel direction respectively. The thickness of the source and drain regions are assumed to be zero for the sake of simplicity of the modeling.

Figure 2 shows the analytical expression of SS along with different parameters for CGAA JLFET. In order to obtain the model for SS, first we determine 2D electrostatic channel potential distribution by solving 2D Poisson’s equation in the channel region using parabolic approximation along radial direction with appropriate boundary conditions. As the device is operating in the subthreshold region, the channel is assumed to be fully depleted. Quantum mechanical effects are ignored for this analytical study. Due to the volume conduction mode of CGAA JLFET the potential along the center line of the channel which is called Body Centered Potential (BCP) plays an important role in the subthreshold region. When minimum BCP becomes zero, a neutral path with bulk silicon is opened along that line in the channel from source to drain direction which is responsible for ON current of the device. So we determine the minimum BCP which is further used to obtain the subthreshold current hence SS for CGAA JLFET.

Figure 3, 4 and 5 shows the variation of SS with the gate length for different gate electrodes, oxide thicknesses and diameters of the channel respectively obtained from the analytical model. For all cases increasing the gate length SS decreases but for CGAA JLFET structure SS cannot be reduced beyond the fundamental limit of 60mV/decade. By increasing the workfunction of gate electrode material, flat band voltage can be increased which decreases SS for CGAA JLFET (Figure 3). On the other hand by decreasing oxide thickness, the gate capacitance can be increased which increases the drain current for the same gate voltage that results decrement of SS (Figure 4). Reduction of channel diameter can also be a method of decreasing SS for CGAA JLFET (Figure 5).

In this work we have developed an analytical model for SS of CGAA JLFET by deriving subthreshold current and 2D channel potential in the subthreshold region using 2D Poisson’s equation and parabolic approximation. The model is further used to make an analysis of performance improvement of subthreshold characteristics for CGAA JLFET. 

References:

[1] Wann et al, IEEE Transactions on Electron Devices, 43(10), pp. 1742-1753 (1996).

[2] Colinge et al, Nature Nanotechnology, 5(3), pp. 225-229 (2010).

[3] Lee el al, Solid-State Electronics, 54(2), pp. 97-103 (2010).

[4] Wang et al, IEEE Electron Device Letters, 34(4), pp. 478-480 (2013).

[5] T. K. Chiang, IEEE Transactions on Electron Devices, 59(11), pp. 3127-3129 (2012).

[6] B. Zhang et al, 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1-3 (2014).

[7] X. Jin et al, Physica Scripta, 89(1), pp. 15804-15809 (2014).