Smart ICT (Information and Communication Technology) such as “Big Data”, “Cloud computing” and Smart Functionalities such as Stand-alone Self-activating MEMS/Sensors construct Smart Systems which enable IoT (Internet of Things), IoE (Internet of Everything) thus Smart Society. To realize above-mentioned Smart Technologies, high-density, low-power consumption, wide-bandwidth, fast-operation semiconductor devices as well as smart functional devices enabled by integrating functionalities with advanced semiconductor technologies including CMOS technologies are necessary. High-density Packaging technologies such as 3D, 2.5D packaging scheme basing on TSV (through-Si via) technology and 2.1D PCB packaging are among key technologies to satisfy the requirements from the both smart semiconductor devices and smart functional devices. "Hetero 3D stacked" technologies are gathering the most attention from now on. These technologies can make a high density packaging interconnection by using TSV on the each function devises. Heterogynous 3D Si integration has great advantages over conventional 2D devices such as high packaging density, small wire length, high-speed operation, low power consumption, and high feasibility for parallel processing. But, the radical problem about the cost of TSV fabrication is not still solved. In particular, the management of barrier metal film deposition on the smooth surface is most important technology for Cu diffuse protection [1]. On the other hand, TSV isolation liner materials with high step coverage and lower temperature deposition on the smooth surface for high frequency devices will be necessary in the future. “Scallop-free” etching process has developed for TSV fabrication [2]. In this paper, our high-density packaging technologies including scallop-free, low-temperature processed TSV solution for via-last packaging scheme and 2.1D packaging solutions on large panel build-up board by semiconductor manufacturer tools will be introduced. Especially, backside Via-last TSV process integration was proposed by “A Novel Dual ICP Plasma” Si etching and low-temperature "Vapor Deposition Polymerization (VDP)" liner (< 200 degree ) for lower-cost and low-stress hetero 3D chip stacked. “A Novel Dual ICP Plasma” is using 2 RF modes mixed ICP plasma. One is high frequency RF mode. And, another is low frequency RF mode. This plasma is able to generate high-density plasma (High etch rate), and also “Scallop-free” smooth etching. This is a kind of “Non-Bosch” process. On the other hand, this dual ICP plasma can carry out “Bosch” process at the same module. This system is very unique etching tool that can use for distinguishing between "Bosch" and "non-Bosch" to TSV cost reduction.