The trench-gated MOSFET is widely used in power management applications because of its ultra-low on resistance [1]. Studies of trench-gate MOSFET reliability and degradation of blocking voltage and leakage current as well as edge termination effects are becoming increasingly important as the device dimensions shrink and its applications are diversified. The HTRB (high temperature reverse-bias) and HAST (highly accelerated temperature & humidity stress test) are often used in reliability assessment of planar discrete power MOSFETs [2] and are currently used in trench-gated MOSFET. The both HTRB stress and HAST stress apply a reverse bias voltage on the drain side with the source and gate grounded at elevated temperature in a MOSFET device. However, the HAST stress is at 85% HR relative humidity under pressure condition. The possible failure modes for HTRB and HAST stress are IDSS (drain to source) leakage current increase or shift, breakdown voltage shift or degradation, and Vth (threshold voltage) shift or instability. The failure mechanism under various failures is complex. They depend on not only device design and process, but also package process and its materials such as mold compound, as well as interaction between device and package.

In this paper, we discuss the instability of n-channel trench-gated MOSFET under HTRB and HAST reliability stresses. The devices are packaged by using state-of-the-art “low pitch” wafer-level-chip-scale package (WLCSP) without the use of mold compound or leads frame. We have observed that the HTRB and HAST stress increases gate oxide interface trap density. However humid HAST stress is observed to further introduce mobile positive charge in the gate oxide of the trench-gated MOSFET. This positive charge is argued to comprise protons (H+s) [3]. The proton is generated through electric-field assisted interaction and hole injection into the gate oxide at the bottom of the trench. The mobility of these protons is observed to cause gate-voltage induced modulation in the threshold voltage and leakage current of the trench-gated MOSFET.

In order to determine the mechanism by which H+s are introduced in the oxide, SEM inspection of the n-channel trench-gated MOSFET deprocessed to passivation showed the presence of passivation cracks in the device’s edge termination which cause moisture penetrated in the device during the HAST stress.

Furthermore, the experimental and simulation results lead us to conclude that in this study we are observing negative bias temperature instability (NBTI) in a parasitic p-MOSFET structure arising at the bottom of the trench in an n-channel trench-gated MOSFET during HTRB stress [4]. The NBTI is enhanced by the presence of moisture in the oxide.

References:

[1]: J. Zeng et al ISPSD 2002, pp. 147-150.

[2]: JEDEC, IESD22-A108D, November (2010).

[3]: J. Hao, M. Rioux, S. Suliman, O. Awadelkarim, Microelectronics Reliability, 54(2014) 374-380.

[4]: J.Hao, M. Rioux, and O. Awadelkarim, IIRW 2011, pp129-131.