It is well known that the top-down fabricated gate-all-around (GAA) silicon nanowire transistor with vertically stacked arrays is promising candidates to replace Finfet devices in sub-10nm nodes. The structure offers optimal electrostatic control, thereby enabling ultimate CMOS device scalability. Silicon nanowire (SiNW) transistors have shown promising potential to revolutionize the area of electronic, optical, chemical, and biological device applications. However, the fabrication of vertically stacked SiNW arrays in a controllable manner remains challenging due to complex topography and geometry characteristics.

Top-down controlled nanowire patterning methods have been developed mostly by Bosch-based process combined with successive stress-limited oxidation. Recently, a more controllable method has been demonstrated to fabricate stacked horizontal nanowires using an epitaxial growth such as Si/SiGe/Si/SiGe structures, but the process requires careful heteromaterial interface handling.

In this work, we propose a simple top-down method to fabricate vertically stacked nanowires arrays on bulk silicon substrates by originally developed process based on a conventional etch tool. Then, the stress-limited oxidation process can be introduced to achieve a uniform shape in a controllable fashion from a bulk silicon wafer. And also, we will discuss some challenges and innovations associated to such structure fabrications.