Capacitance of Graphene/Copper Hybrid Nano Ribbon Interconnect - a First Principle Study

Thursday, 1 June 2017: 15:00
Churchill A1 (Hilton New Orleans Riverside)
K. M. Mohsin, A. Srivastava (Louisiana State University), A. K. Sharma, and C. Mayberry (United States Air Force Research Laboratory)
In very large scale integration (VLSI), as the Moore’s law is nearly to end, researchers are in search for alternative interconnect materials with excellent electrical and thermal conductivities. Various emerging reduced dimensional materials are under study to find an alternative to the Cu-based interconnect for post-CMOS technology nodes. In this regard, graphene (G) and carbon nanotubes (CNT) have been studied extensively in last decade. Since graphene and CNT have their own limitations in integrating with present CMOS technology, there is ongoing research to find hybrid materials, which can have simultaneously better thermal and electrical conductivity [1]. Recently, reduction in temperature has been observed in graphene encapsulated Cu wires [2] and potential application of graphene as a heat spreader. Since Cu-based VLSI interconnect is already in use in current CMOS technology it would be easier to integrate graphene as a Cu barrier layer and the heat spreader. Low-cost CVD techniques for large area graphene deposition on Cu film are well known. Graphene deposition on Cu includes an annealing process which eventually increases crystal integrity of Cu with larger grain size. In addition, graphene works as a barrier layer for Cu ion to diffuse into the dielectric. This is why G/Cu hybrid interconnect is a very good case for investigating electronic properties. Motivated by recent experiments, we have studied theoretically G/Cu structure in bulk and in one-dimension (1D) as next generation wire for nano-electronic applications. Our purpose is to investigate electronic properties of this structure with density functional theory (DFT). In this paper, we report density of states (DOS) and the quantum capacitance of (CQ) of G/Cu nanoribbon interconnect.

We used DFT to study electronic band structure within Quantum-Espresso (QE) code. QE calculation is based on self–consistent plane-wave with Perdew-Zunger (PZ) pseudo-potential. We have considered one-dimensional slice of G/Cu interconnect of width 5nm, height 0.8nm and a variable length. A single layer of graphene is deposited on top of three atomic layers of Cu {111}. Cu {111} is chosen because this plane is closest to graphene lattice within 2% lattice mismatch. Among these three atomic layers, bottom two layers were fixed to their bulk lattice positions to represent bulk atoms. Top Cu layer and graphene layer were relaxed to find minimum force position. After obtaining atomic positions from relaxation calculations in QE, we performed self-consistent field calculation and band structure calculation. Details of DFT calculation is reported in our earlier work [3]. From electronic band structure, the electron density of states (DOS) is calculated. CQhas been calculated from DOS.

C-V characteristics of a 5nm wide G/Cu nanoribbon interconnect (1D) is computed and also compared with G/Cu 2D case. For the purpose of comparison, we calculated quantum capacitance per unit area for both 1D and 2D cases. We have observed significant enhancement of CQ in G/Cu nanoribbon from its 2D counterpart. More electrons tunnel from underlying Cu substrate to graphene layer which cause more carrier density and enhances CQ. Dirac point shifting is also observed which is due to work function difference of G and Cu. Because of Dirac point shifting minimum capacitance point is also shifted from charge neutrality point. Near charge neutrality point, CQis nearly “V” shaped as in graphene but minimum capacitance is non-zero unlike graphene. This calculation is very useful in understanding electrical performances of G/Cu nanoribbon interconnect towards finding a suitable candidate of next generation interconnect materials. Due to enhanced capacitance, beside VLSI interconnect application, this work can be used for charge storage devices also.

 Acknowledgement:Part of this work is supported by the United States Air Force Research Laboratory under agreement number FA9453-10-1-0002. The U. S. Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation thereon. Portions of this research were conducted with high performance computing resources provided by Louisiana State University (http://www.hpc.lsu.edu).

[1] P. Goli, H. Ning, X. Li, C. Y. Lu, K. S. Novoselov, and A. A. Balandin, “Thermal Properties of Graphene–Copper–Graphene Heterogeneous Films,” Nano Letters,vol. 14, no. 3, pp. 1497-1503, April 12, 2014.

[2] R. Mehta, S. Chugh, and Z. Chen, “Enhanced Electrical and Thermal Conduction in Graphene-Encapsulated Copper Nanowires,” Nano Letters,vol. 15, no. 3, pp. 2024-2030, March 11, 2015.

[3] K. M. Mohsin, A. Srivastava, A. K. Sharma, C. Mayberry, and M. S. Fahad, “Current Transport in Graphene/Copper Hybrid Nano Ribbon Interconnect: A First Principle Study,” ECS Transactions, vol. 75, no. 13, pp. 49-53, August 25, 2016.