Simulation results show the abrupt VTH increase is caused by a combined effect of bulk and front/back interface trap charges. As scaled down, yet the bulk trap density decrease, VTH is increased as it is overturned by front and back interface trap charge effects. Compared to front interface trap charges, back interface trap charges have larger influence on VTH. Since device with ts below 10nm is fully depleted before the gate voltage reaches VTH, the additional electric field formed across the poly-Si channel parallel shifts the band downwards. So the more parallel shifted the band is, the more additional portion of the front and back interface is filled with negative charge. As a result back interface charges increase VTH. The closer it gets to the channel, greater the influence become. It is quite clear why back interface trap charges contribute more to the VTH, compared with front interface trap charges.
The simulation results considering bulk and front/back interface trap effects showed a good match experiment results. Considering the abrupt VTH increase and variation of poly-Si deposition process, the fundamental criterion of poly-Si thickness scaling limit should be no lower than 5nm.