The widely anticipated end to Moore’s law and the growing demand for low power computing systems capable of learning, image recognition and real-time analysis of large streams of unstructured data has spurred intense interest in neural algorithms for brain-inspired computing. The brain is capable of massively parallel information processing while consuming only ~1- 100 fJ per synaptic event. Inspired by the efficiency of the brain, CMOS-based neural architectures and tunable resistance elements (memristors) are being developed for low-power pattern recognition and machine learning. However, the volatility, design complexity and high supply voltages for CMOS architectures on one hand, and the stochastic and energy-costly switching of memristors on the other significantly complicate the path to achieve the extreme interconnectivity, information density, and energy efficiency of the brain using either approach. To overcome these limitations, we have recently demonstrated a Li-ion synaptic transistor for analog computation (LISTA).¹ LISTA is an all solid-state, non-volatile redox transistor (NVRT) with a resistance switching mechanism based upon the intercalation of Li-ion dopants into a channel of Li_1-xCoO₂. An NVRT differs from previously described electrochemical transistors in that dopants cannot diffuse out of the channel (after relaxation of applied bias) without an external source of charge to facilitate oxidation and liberate them as ions in a surrounding electrolyte. This is identical to the charge storage mechanism in batteries, which require external current sources to drive charge/discharge redox reactions. A major advantage of the LISTA device is that resistance switching can occur without inducing large structural transformations that are common for memristive devices, such as filament formation or amorphous-to-crystalline phase transformation. In my talk I will show that the structurally stable, diffusion-driven switching mechanism of Li intercalation allows LISTA to operate with a low ‘write’ noise, a near linear response to ‘write’ operations, and orders of magnitude lower switching voltages and currents. Furthermore, our simulations of the device physics demonstrate that scaled LISTA devices will have orders of magnitude lower energy consumption than any resistive memory device to date, and could operate as part of a neural architecture with an energy efficiency matching the brain. Finally, I will introduce an NVRT device based entirely on organic polymers fabricated on flexible substrates. Such devices could in principle form direct interfaces with the brain opening up the opportunity to build advanced neural prostheses with integrated brain-machine interfaces.

1.Fuller, E. J.; Gabaly, F. E.; Léonard, F.; Agarwal, S.; Plimpton, S. J.; Jacobs-Gedrim, R. B.; James, C. D.; Marinella, M. J.; Talin, A. A., Li-Ion Synaptic Transistor for Low Power Analog Computing. Advanced Materials 2016, DOI: 10.1002/adma.201604310