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Automotive Pouch Cell Performance: Effect of Silicon Loading, Binder, and Additives

Monday, 29 May 2017: 11:40
Grand Salon C - Section 15 (Hilton New Orleans Riverside)
M. Karulkar, H. Wen, R. Blaser, R. Kudla, and A. Drews (Ford Motor Company)
As the auto industry looks towards increased electrification, there is a clear need for higher energy density batteries to increase vehicle range. One of the most promising next-gen anode materials is silicon, and indeed it is already being implemented in consumer electronic cells. [1] The first use in automotive cells will likely be lower-loading silicon in graphitic anodes. In anticipation of silicon incorporation in automotive applications, it is important to consider volume expansion of such cells. Existing automotive battery designs cannot accommodate significant volume expansion. There are also continuing concerns about cycle life and first cycle capacity loss. Factors like binder, electrolyte additives, and silicon content strongly affect performance metrics. [2]

To address these issues, 2 Ah and 4 Ah pouch cells were fabricated with NMC cathodes and various anode formulations, including 5% and 10% silicon in graphite, CMC/SBR and PAA binders, and with electrolytes containing 10% and 25% FEC additive. These cells were fabricated at the University of Michigan battery lab, and tests were conducted in-house. Design constraints, which will be discussed in this talk, limited N:P ratios to relatively high values (>1.5), which highlights challenges to designing full cells with high-SEI forming materials. PAA was found to produce 20% better capacity retention at 100 cycles, though that advantage lessened with continued cycling beyond 250 (Figures 1 and 2). Electrolyte with 10% FEC produced markedly better performance (40% + better retention) for the 5% silicon anodes. 25% FEC electrolyte produced better performance for higher-silicon anodes with 10% silicon. Volume expansion depended strongly on silicon content, but in no cases did cells swell by more than 2%, which is within current tolerances for pack design (Figure 3). The results point to future work with increased silicon content and more optimized N:P ratios that approach unity.

[1] X. Zuo, J. Zhu, P. Müller-Buschbaum, Y. Cheng, J. Power Sources, 31, 113-143 (2017).
[2] M. Karulkar, H. Wen, R. Kudla, R. Blaser, ECS Transactions, 72, 197-206 (2016).