Even with the copious advances in logic device fabrication, integration of new channel materials would represent a significant advance in CMOS technology. [1] Successful integration of new channel materials (III-V’s, Ge and SiGe) pose significant challenges for etch technology. Dry (plasma) etch technology can be used to pattern channel materials after they are deposited using an epitaxial process [2]; alternatively channels maybe inserted into bounded (for example an oxide) recesses (for example silicon) fabricated using etch technologies already developed for FinFET and SAQP applications. Less appealing is the use of wet processes that have troublesome crystallographic orientation dependencies. Dry etch technology for most new channel material candidates is not new. [3] Still, with dry etch technology there is the ever-present worry of damage. [4-6] High precision etch technology commonly referred to as atomic later etching (ALE) is an emerging viable option for new channel material integration. [7-10] Some approaches employ non-mainstream techniques such as neutral beam technology [8] or complex precursors. [10] Recent developments reinforce that conventional plasma etch technologies developed using concurrent engineering methods can meet the requirements for 7 and 5 nm logic fabrication. [7,11] This presentation will show how advanced plasma etch technologies provide a path for logic manufacture beyond 7 nm with a realistic picture of the trade-offs that must be handled for the introduction of III-Vs, Ge or SiGe. All in all, etch technologies if successfully implemented for new channel material integration relies of leveraging surface chemistry mechanisms. The presentation will be rounded out with a discussion of how first-principles methods (e.g., DFT methods) can be used to gain insight into important plasma –surface interaction mechanisms.

1. S. Takagi et al., Japanese Journal of Applied Physics 54, 06FA01 (2015)

2. Chen et al,. Nanoscale Research Letters, 7, 431 (2012)

3. Plasma Etching of III–V Nitrides,” by R. Shul, in Processing of Wide Band Gap Semiconductors: Growth, Processing and Applications, 250 (2000), ed., S.J. Pearton

4. F.D. Auret et al., Physica B, 407, 1497 (2012)

5. Kasumandari et al., Appl. Phys. Lett., 103, 033511 (2013)

6. “Dry Etching of Semiconductors at the Nano-and Micro-Scale” by S.J. Pearton in Vistas in Nanofabrication, (2012)

7. A. Ranjan et al., J. Vac. Sci. Technol. A 34, 031304 (2016)

8. S.D. Park et al., Appl. Phys. Lett. 91, 013110 (2007);

9. C. T. Carver et al., ECS J. Sol. St. Sci. Tech., 4 N5005-N5009 (2015)

10.  S. M. George, Chem. Rev., 110, 111 (2010)

11.  S.D. Sherpa et al., J. Vac. Sci. Technol. A 35, 01A102 (2017)