Based on the work function difference between the NW and the deposited metal clusters, the carrier concentration of device channels could be modulated accordingly, and as a result the VTH of different III-V NW transistors can be adjusted efficiently toward positive or negtive position . It shoud be noted that these fabricated transistors had limited air stability due to the rapid oxidation of decorated metal clusters in the ambient environment. Therefore, a thin layer of Al2O3 was needed to passivate the metal clusters from oxidation, which could possibly limit their uses of NEFETs in certain application fields. In addition, we have as well employed thiolate-based aromatic monolayers with controllable molecular structure and electron density to modify the surface carrier concentration of InAs NW channels, resulting in manipulatable changes of the device VTH . What’s more, the electron mobility and the current on off ratio is also improved greatly. To our disappointment, because of the sensitivity of these organic molecules to oxygen and humidity, this chemical passivation approach of NWFETs was again unstable in the ambient. Additionally, it should be noted that since the electron withdrawing or donating effect of thiolate-based aromatic monolayers were limited, the resulting device VTH could only shift with a relatively small range from 0.25 to 1.57 V. In the following, the free electrons in the NW channel (i.e. InAs, InP and InGaAs) can be modulated effectively via depositing various metal-oxide (NPs) with different work functions. Without any passivation layer, this decoration approach can yield the stable NW device characteristics in ambient. Notably, the versatility of our decoration scheme has also been illustrated through the realization of high-performance enhancement-mode InAs NW parallel arrayed devices as well as the configuration of highly efficient InAs NW NMOS inverters, comprising of both depletion and enhancement mode devices. All these results further elucidate the technological potential of this decoration approach for future high-performance, low-power nanoelectronic device fabrication and circuit integration.
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