(Invited) MOS Interface Defect Control in Ge/III-V Gate Stacks

Tuesday, 3 October 2017: 10:20
Chesapeake D (Gaylord National Resort and Convention Center)
S. Takagi, M. Ke, C. Y. Chang, C. Yokoyama, M. Yokoyama, T. Gotow, K. Nishi, S. Yoon, and M. Takenaka (The University of Tokyo)
One of the most critical issues for realizing high performance Ge/III-V CMOS, which can be regarded as one of the promising device structures in the future technology nodes, is to establish the gate stack technologies simultaneously satisfying many requirements such as thin EOT, low interface state density (Dit), low slow trap density (Dtrap), high channel mobility and high gate insulator reliability. For this purpose, basic understanding of Ge/III-V MOS interfaces including physical origins of interface defects and the influence on channel mobility is indispensable.

In order to realize low Dit, high channel mobility and thin EOT for Ge MOSFETs, we proposed an interfacial layer (IL) formation process employing ECR plasma post oxidation to form ultrathin GeOx through thin ALD Al2O3 [1, 2] or HfO2/Al2O3 [3]. By using the HfO2/Al2O3/GeOx/Ge gate stacks, Ge n- and p-MOSFETs (EOT of 0. 76 nm) with high electron (690 cm2/Vs) and hole (550 cm2/Vs) peak mobility were obtained. However, one of the most difficult challenges for the present GeOx-based ILs is the existence of high Dtrap [4, 5]. The slow traps can exist near GeOx/Ge interfaces, because the trapping characteristics are almost insensitive to the thickness of GeOx and Al2O3 [6]. Recently, inclusion of Y atoms into GeOx has been reported to effectively suppress Dtrap [7, 8]. We are currently working for the reduction in Dtrap by suing the ALD AlYO3/GeOx or Y2O3/GeOx interfaces [9, 10]. While the impact is still limited at present, further improvement in Dtrap is expected.

For III-V MOS interface control, understanding of III-V MOS interface defects and establishment of the MOS interface defect control technologies have not been fully obtained yet. There still remain many issues, such as (1) higher Dit and Dtrap at InGaAs MOS gate stacks with Al2O3-based ILs than in Si and Ge MOS gate stacks (2) inferior MOS interface properties on Sb-based materials such as GaSb, GaAsSb and InGaSb (3) poor MOS gate stack reliability [5, 11, 12].

We studied the impact of ALD La2O3/InGaAs MOS interfaces on the performance of InGaAs MOSFETs. It was found that La2O3/InGaAs MOSFETs exhibit lower S. S. and lower carrier trapping properties, while have lower mobility than Al2O3/InGaAs MOSFETs because of higher fixed oxide charge density. Also, it was experimentally found that ALD La2O3 films with thermal budget lower than 300 oC have ferroelectricity in W/La2O3/InGaAs MOS and W/La2O3/W MIM structures. The steep slope characteristics due to the negative capacitance effect have been demonstrated in W/La2O3(15nm)/InGaAs MOSFETs [13]. We also found that BHF/HF pre-treatment is more effective for reduction of the fast interface state density at ALD Al2O3/InxGa1-xAs with higher In content (x=0.7 and 1) in comparison with conventional (NH4)Sy pre-treatment [14, 15]. It was suggested through the XPS analyses that the reduction in Dit is attributable to the dominance of As dangling bonds on Dit with higher In content and the effective passivation of oxygen atoms with these dangling bonds.

For GaSb and GaAsSb MOS interface control, ultrathin InAs and InGaAs surface passivation layers have been found to be effective in reducing the fast interface state density [16, 17]. However, the detailed studies on further reduction in Dit and Dtrap and understanding of the relationship between the channel mobility and the interface properties are still strongly needed for Sb-based MOS devices.

This work was partly supported by JST-CREST and the Grant in-Aid for Scientific Research through the MEXT (26249038). The authors would like to thank Drs. M. Yokoyama, H. Yamada and T. Yamamoto in Sumitomo Chemical Corporation, and Drs. M. Mitsuhara, H. Sugiyama, T. Hoshi and H. Yokoyama in NTT for their collaborations.

References [1] R. Zhang et al., APL. 98, 112902 (2011) [2] R. Zhang et al., TED 59, 335 (2012) [3] R. Zhang et al., TED 60, 927 (2013) [4] R. Zhang et al., IEDM, 642 (2011) [5] G. Groeseneken et al., IEDM, 828 (2014) [6] M. Ke et al., APL. 109, 032101 (2016) [7] C. H. Lee et al., IEDM, 40 (2013) [8] C. Lu et al., IEDM 370 (2015) [9] M. Ke et al., Microelectron. Eng. 147, 244 (2015) [10] M. Ke et al., to be presented in Microelectron. Eng. (2017) [11] S. Deora et al., IEEE TDMR, 507 (2013) [12] J. Franco et al., IRPS, 6A2 (2014) [13] C.-Y. Chang et al., IEDM, 322(2016) [14] K. Nishi et al, APEX. 8, 061203 (2015) [15] C. Yokoyama et al., EDTM, 23 (2017) [16] M, Yokoyama et al., APL. 106, 122902 (2015) [17] T. Gotow et al, SISC, 6. 3. (2016)