(Invited) High-K Dielectrics: A Perspective on Applications from Silicon to 2D Materials

Monday, 2 October 2017: 10:00
Chesapeake D (Gaylord National Resort and Convention Center)
R. M. Wallace (University of Texas at Dallas)
In the 1990’s, research accelerated on addressing the limits of the industry standard gate dielectric: SiO2. With the most aggressive integrated circuit scaling, it became clear that standby power for MOSFETs required the insertion of a gate dielectric material that reduced tunneling leakage while enabling performance expectations. Leveraging prior dielectric research and after exploring several dielectric material candidates, [1,2] Hf-based dielectrics became the dominant choice and were established in commercial Si technology fabrication processes in 2007 after at least a decade of research. [3] Although perhaps forgotten among today’s 3D FET technologies, the introduction of a new gate dielectric, simultaneously with metal gate materials, was considered quite revolutionary in its day, and this development, in conjunction with other device engineering aspects like strain, enabled the continued march of industry along Moore’s original predictions. Since that time, the research on incorporating high-k dielectrics has expanded to address alternative channel materials including Ge, III-V, wide band gap semiconductors, and, most recently, perhaps the ultimate limit in channel scaling – atomically thin 2D materials. This talk, from the author’s perspective, will review some of these developments, many presented at the annual ECS high-k gate dielectric symposia led by Prof. Kar, and provide some context on the resilience of the materials research as well as the challenges and opportunities that lie ahead.

This work is supported in part by: (i) the SWAN Center, a SRC center sponsored by the Nanoelectronics Research Initiative and NIST, (ii) the Center for Low Energy Systems Technology (LEAST), one of six centers supported by the STARnet phase of the Focus Center Research Program (FCRP), a Semiconductor Research Corporation program sponsored by MARCO and DARPA, (iii) the US/Ireland R&D Partnership (UNITE) under the NSF award ECCS-1407765, and (iv) the Erik Jonsson Distinguished Chair in the Erik Jonson School of Engineering and Computer Science at the University of Texas at Dallas.

[1] J. Robertson and R.M.Wallace, “High-K materials and metal gates for CMOS applications,” Materials Science and Engineering R, 88, 1-41 (2015)

[2] G.D.Wilk, R.M.Wallace, and J.M.Anthony, “High-k Gate Dielectrics: Current Status and Materials Properties Considerations”, Journal of Applied Physics 895243 (2001)

[3] M.T. Bohr, R.S. Chau, T. Ghani, K. Mistry, “The High-k Solution,” IEEE Spectrum. 44 (29) (2007).