828
(Invited) Modifying Silicon/Dielectric & Silicon/Metal Interfaces Using Sub-2 Nm Pt Nanoparticles

Tuesday, 3 October 2017: 09:29
Chesapeake D (Gaylord National Resort and Convention Center)

ABSTRACT WITHDRAWN

Understanding the nature/density/energy levels of interface traps at Si/dielectric and Si/metal interfaces is essential towards producing reliable functioning devices. Typically high temperature post processing H2 anneals are utilized in industry to reduce these interface traps, but stability of these H passivated traps is questionable, especially if the device undergoes other high temperature processes downstream. Our studies show that by utilizing sub-nm Pt nanoparticles at Si/dielectric and Si/metal interfaces the degree of fermi-level pinning can be modulated. These sub-nm Pt nanoparticles can be used to modify metal/Si contact barrier in combination with either a 0.98 nm Atomic Layer Deposited Al2O3 or a 1.6 nm chemically grown SiO2 dielectric layer, or both. We have studied the role of these Pt NP’s size dependent properties, i.e., the Pt NP-metal surface dipole, the Coulomb blockade and quantum confinement effect in determining the degree of Fermi level depinning observed at the studied metal/p-Si interfaces. By varying only the embedded Pt NP size and its areal density, the nature of the contact can also be modulated to be either Schottky or Ohmic upon utilizing the same gate metal. 0.74 nm Pt NPs with an areal density of 1.1 × 1013 cm−2 show ~382 times higher current densities compared to the control sample embedded with similarly sized Pt NPs with ~1.6 X reduction in areal densities. We further demonstrate that both Schottky (Ti/p-Si) and poor Ohmic (Au/p-Si) contact can be modulated into a good Ohmic contact with current density of 18.7 ± 0.6 A/cm2 and 10.4 ± 0.4 A/cm2, respectively, showing ~18 and ~30 times improvement. A perfect forward/reverse current ratio of 1.041 is achieved for these low doped p-Si samples. In addition, we have also explored the influence of Pt NP-induced border traps within dielectrics near Si surface and the surface coverage dependent pinning of embedded Pt NP work function. The pinning of these nanocrystal work-function was found to be induced by a high density of dangling bonds near the Pt NP/Al2O3 interface which skews the expected charging/discharging characteristics with electron programming favored over holes. The degree of this pinning was probed utilizing C–V measurements and seems to be dependent on the density of Al2O3 dangling bonds near Pt NP surface. This density of dangling bonds acting as border traps has been observed as an increasing function of the Pt NP surface percent coverage. Gaining adequate understanding the location, energy, and positioning of the energy levels of these defects at the metal/high-k interface relative to Si band gap can help overcome poor retention and leakage issues that typically compromise the performance of new generation memory devices.