P-type SOI(88 nm)/BOX(145 nm) wafer was cleaned with SPM and HF solutions. For heavily-doped n-type SOI (n⁺ SOI), phosphorus-doped spin-on-glass (SOG) was deposited with spin coating and baked on a hot plate at 180 ^oC. The substrate was annealed at 1000 ^oC in N₂ for 30 min to perform solid phase diffusion. Then, SOG was removed by 1 % HF for 30min. For heavily-doped p-type SOI (p⁺ SOI), B⁺ ions were implanted into SOI layer. Activation was performed at 1000 ^oC in Ar for 30 min. SOI layer was patterned by chemical dry etching with CF₄/O₂. Thermal SiO₂ was grown by dry oxidation at 900 ^oC for 10 min. Next, AlO_x was deposited by RF sputtering. After contact opening with 1 % HF, Al (20 nm)/TiN (20 nm) were deposited by RF sputtering and lift-off for electrical contact to SOI. The substrates were subjected to annealing in forming gas at 420 ^oC for 30 min to improve the quality of gate dielectrics and electrical contact of gate pad. Al (10 nm)/Au (40nm) was deposited by thermal evaporation and lift-off for contact electrodes. Subsequently, the substrate was exposed to oxygen plasma to form hydroxyl groups on the surface of AlO_x. Then, the substrate was immersed into 2-propanol containing 5 mM n-octadecylphosphonic acid (ODPA) for 6 hours at room temperature. Annealing was conducted at 100 ^oC in N₂ for 30 min to stabilize ODPA. The gate dielectrics consists of hybrid ODPA/AlO_x/SiO₂. Mechanically exfoliated WS₂ was transferred to the substrate with the PDMS elastomer. Finally, devices were annealed in N₂ at 150 ^oC for 30 min to improve source/drain contact.

The FET operation was observed for both n⁺ and p⁺ SOI gate. The threshold voltage (V_th) was evaluated by linear extrapolation method with the drain current measured as a function of gate voltage at a low drain voltage of 0.05 V. In the case of n⁺ SOI gate electrode, the V_th of -0.71 V, On/Off ratio of 10³～10⁴ and subthreshold slope (SS) of 150 mV/dec were evaluated. On the other hand, the V_th of -0.13 V, On/Off ratio of 10³～10⁴ and subthreshold slope (SS) of 107 mV/dec were obtained for p⁺ SOI gate electrode. The difference in V_th between n⁺ and p⁺ SOI gate electrodes is derived from the difference in the Fermi level of SOI. The proposed method is suited for research in electrical characteristics of various TMDC semiconductors.