For integration of III-V NWs on Si, selective-area growth has no thick buffer layer, thus the III-V NWs/Si interface is able to show unique band structures. The narrow gap III-Vs such as InAs and In0.7Ga0.3As NWs, for instance, exhibits staggered-Type II band structure when the n-type NWs are formed on p-Si substrates regardless precise doping. Thus, we integrated InGaAs NWs on Si substrate by utilizing specific growth sequence to align vertical NWs . Sn was used for n-type dopant, and Zn-pulse doping technique  was used to make pseudo intrinsic layer as channel region. The formation of intrinsic layer in such small NW-volume would be very important to induce large internal electrical field at the InGaAs/Si heterojunction. The length of the Zn-pulse doped region correspond to channel-length (200 nm-long in this case).
Next, we demonstrate electronic devices using III-V NWs on a Si substrate. Fabricated vertical transistors contained In0.7Ga0.3As NWs with modulation doped layer. We observed n-type FET behavior in ID-VDS and ID-VG characteristics. The performances are threshold voltage ~ 0.25 V, Gm,max = 1.45 µS/µm at VDS = 0.50 V, Ion / Ioff > 106, subthreshold slope, SS = 78 mV/decade.
Besides the III-V NW-based vertical FETs, the heterointerface between the III-V NWs and Si can be used as tunnel FETs (TFETs). In this case, we use band discontinuity between III-V NWs and Si substrate for TFETs. The device fabricated by InAs NW on Si substrate showed switching behavior with an average subthreshold slope (SS) of 30 mV/dec, which is much lower than the physical limitation of metal-oxide-semiconductor field-effect transistors (MOSFETs, SS ~ 60 mV/dec.) [8,9]. Reducing the opening diameter of the masked substrate decreased the numbers of misfit dislocations. The TFETs made by using III-V NW/Si heterojunctions demonstrated steep-SS properties at room temperature. One of the key issues in the vertical TFETs is the formation of intrinsic channels inside the tiny NW-body and another is the reduction of NW-diameter. We also discuss several current-boosting technologies for the TFETs. The current-boosted TFET exhibits steep SS and high Ion, and the transconductance efficiency (Gm/ID), which is important parameter for low-power analog circuits, is a thousand times higher than that of conventional MOSFETs .
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10) K. Tomioka et al., paper submitted