Ge has been considered as an alternative channel material in place of Si because of its higher electron and hole mobility. Since direct deposition of high-k material on Ge leads to degradation of interface quality ultrathin Al₂O₃ is used as a passivation layer prior to high-k layer deposition. In addition, ZrO₂/Al₂O₃ bilayer as gate dielectric on Ge is becoming popular since ZrO₂ showed lower leakage current than HfO₂ (1, 2). To further scale the effective oxide thickness (EOT) on Ge higher-k dielectric materials like Hf_1-xZr_xO₂, with different Hf to Zr compositions has been explored. Furthermore, the recent introduction of post-deposition slot plane antenna plasma oxidation (SPAO) of the dielectric seems to enhance the interface as well as gate stack quality (3).

In this work, we investigate the Time Dependent Dielectric Breakdown (TDDB) characteristics of the impact of TiN/ Hf_xZr_1-xO₂/Al₂O₃/Ge gate stacks by changing the Zr content. Slot-plane antenna plasma oxidation (SPAO) was performed on these devices after the ALD deposition of the high-k layers. It was observed that the equivalent oxide thickness (EOT) decreases with Zr addition in HfO₂ with up to 75% of Zr incorporation. With 100% Zr incorporation EOT increased significantly. This is possibly due to the formation of low-k interfacial GeO₂ at the interface for 100% Zr whereas for other samples have comparatively thinner GeO_x interfacial layers (3). Weibull plots shows that charge to breakdown (Q_BD) increased with increase the Zr percentage. However, the breakdown acceleration factor decreased with Zr percentage up to 75% and increased rapidly for 100% Zr content. It is reported earlier (3) that GeO₂ has the worst resistance to stress in terms of device stability compared to GeO_x. Therefore, formation of thick GeO₂ degrades the device with 100% Zr rapidly as compared to lower percentage of Zr.

The authors would like to acknowledge K. Tapily, R. D. Clark, S. Consiglio, C. S. Wajda, and G. J. Leusink of TEL Technology Center, Albany, NY for their help in device preparation.

References:

1. X.-F. Li et al, ECS Solid State Letters 1 (2), N10-N12 (2012).
2. M. N Bhuyian et al, ECS Journal of Solid State Science and Technology 3 (5), N83-N88 (2014).
3. Y. Ming et al, IEEE Transactions on Device and Materials Reliability, DOI: 10.1109/TDMR.2017.2681428