In one set of experiments, a temperature dependent border trap response for Al2O3 gate dielectrics is investigated. This behavior is unexpected for defects that have typically been reported to charge and discharge through direct tunneling of electrons from the n-type substrate. Temperature dependent border trap frequency dispersion of the accumulation capacitance and conductance is found to be correlated with the presence of a defective interfacial layer, which can be intentionally produced either by excessive exposure to hydrating or oxidizing species during atomic layer deposition of Al2O3 or by use of a previously-reported aqueous HCl wet clean of the InGaAs surface prior to ALD. These results point out the sensitivity of the temperature dependence of the border trap response in metal oxide/III-V MOS gate stacks to the presence of processing-induced interface oxide layers, which alter the dynamics of carrier trapping at defects that are not located at the semiconductor interface.
We also report on the effects of pre- and post-atomic layer deposition (ALD) defect passivation with hydrogen on the trap density and reliability of Al2O3/InGaAs gate stacks. Reliability is characterized by capacitance-voltage hysteresis measurements on samples prepared using different fabrication procedures and having different initial trap densities. Despite its beneficial ability to passivate both interface and border traps, a final forming gas (H2/N2) anneal (FGA) step is found to induce a significant hysteresis. This is caused by hydrogen depassivation of defects in the gate stack under bias stress, supported by the observed bias stress-induced increase of interface trap density, and strong hydrogen isotope effects on the measured hysteresis. Additional strategies, beyond hydrogen annealing, for more stable interface defect passivation on InGaAs will be discussed briefly.