Half a decade ago we have witnessed a paradigm shift in CMOS technology. After more than forty years of planar device architecture serving logic industry, a need for improvement of scaling behavior of such transistors went beyond capability of traditional design knobs: dielectric thickness, supply voltage, doping of the device. Long researched FinFET transistor came to the rescue with a launch of Intel’s Ivy Bridge microprocessor in 2012.

FinFET’s fully-depleted operation of thin, largely undoped body substantially surrounded by the gate, brought about significant improvement of device electrostatic behavior which led to better control of off-current while enabling better drive current at smaller gate lengths [1]. Smaller gate lengths facilitated extension of CMOS scaling into, by now, a third generation beyond last planar technology of 32nm (28nm) node. Multiple innovations assisted FinFET architecture in its scaling path, from further traditional thinning of gate’s high k dielectric and more aggressive source-drain doping engineering and buildup of stress, to self-aligned contact schemes, to thinner, straighter and taller fin profile.

FinFETs are likely to afford us another node of (2D) technology scaling before being replaced by more scalable alternatives.

While FinFETs have firmly been established as mainstream CMOS logic technology today, there is an alternative fully depleted device, with planar configuration, which finds itself a space in the advanced logic market. Fully-depleted planar SOI devices have less scaling potential than FinFET, however, it offers a unique device feature - back-bias – that enables post-process tunability of performance, while delivering competitive cost per wafer [2].

Nanowire, or gate-all-around (GAA) transistors, offer yet further improvements of electrostatic control of the channel that promises to extend scaling of CMOS beyond FinFETs [3]. A natural extension of FinFET geometry, horizontal nanowire (hGAA), is generally proposed in stacked configuration of 2-3 wires to make up for lesser drive current per footprint than that offered by FinFET. The potential for scaling is somewhat limited with gate length allowed to shrink by only a few nanometers for similar performance to FinFET.

Transition from hGAA to vertical GAA (vGAA) devices releases this constrain. Current in vGAA flows orthogonally to wafer surface. That allows more conservative scaling of vGAA gate length and thus enables further density scaling of devices [4]. However, it does not offer improvement of drive current per footprint available to hGAA thru nanowire stacking. Careful analysis of parasitics and placement of devices in low-track-count standard cell designs will determine how much scalability will be available with GAA devices.

Vertical stacking of devices (3D) provides another alternative to scaling where increased device areal density can be realized at the same design rules. A so called sequential 3D or monolithic 3D forms two or more vertically stacked tiers of devices thru transfer of blanket SOI film onto a standard wafer with fully processed devices [5]. Thickness of SOI is sufficient to maintain patterning overlay common for standard CMOS - of a few nanometers. The approach also promises improved performance thru significant reduction of interconnect wire length.

Group III-V and Ge looked attractive from bulk material transport properties perspective for replacement of silicon in the channel. However, several findings about those materials suggest that they will likely not supplant silicon on CMOS scaling path.

A new material, ferroelectric, applied in the structure of MOSFET gate dielectric has been shown to exhibit negative capacitance that can substantially improve device performance (both electrostatics and transport) regardless of its architecture. Those devices are known as negative capacitance FETs (NCFET) [6].

Finally we will also look at some examples of devices beyond classical drift diffusion of electrons and holes: tunnel FETs (TFET), spin-based devices and others. All have interesting features to offer with potential for niche applications. However, at this point none seems to be able to challenge Si-based technology for scaling CMOS in the next decade (Fig.1).

1. Collaert et al, “Tall Triple-Gate Devices with TiN/HfO₂ Gate Stack”, Symp. VLSI Tech. Dig., p. 108 (2005)
2. Carter et al, “22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications”, IEDM, p.27 (2016).
3. Jang et al., “Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node”, TED 64(6), p.2707 (2017)
4. Yakimets et al. “Vertical GAAFETs for the Ultimate CMOS Scaling”, EDL 62(5), p.1433 (2015)
5. Batude et al., “Advances in 3D CMOS Sequential Integration”, IEDM, p.345 (2009).
6. H.Lee et al., “Physical Thickness 1.x nm Ferroelectric HfZrOx Negative Capacitance FETs“, IEDM, p.307 (2016)