The junctionless (JL) device concept for silicon-on-insulator MOSFETs was introduced by Colinge et al. in 2010 [1], demonstrating considerable gains in terms of process simplicity when compared to conventional inversion-mode MOSFETs. The objective of this work is to implement the JL device concept in an In_0.53Ga_0.47As channel, where the SiO₂ insulator in [1] is replaced by a wider bandgap p-type In_0.52Al_0.48As barrier layer and to investigate the effect of low-temperature RF hydrogen plasma treatment on the main electrical parameters of such devices. The JL device architecture is particularly well suited to III-V channel materials. Firstly, the high doping concentration (N_d) present in the channel of a JL MOSFET is less problematic for In_0.53Ga_0.47As than it is for Si. Indeed, the bulk electron mobility in Si is ~100 cm²/V·s at N_d = 1×10¹⁹ cm^-3, while in In_0.53Ga_0.47As the bulk mobility is ~4,000 cm²/V·s at a similar N_d level. Moreover, the JL architecture circumvents the difficulties associated with the implantation or regrowth techniques generally used to form the source/drain (S/D) regions of III-V inversion-mode MOSFETs. However in order to form a good Ohmic S/D contacts it is necessary to anneal the device at 350-400°C that could lead to diffusion of In atoms into the gate dielectric. In this work low-temperature RF plasma treatment (RFPT) [2] is proposed to improve S/D contacts and enhance the properties of JL MOSFETs.

A structure consisting of a 32-nm-thick n- In_0.53Ga_0.47As (N_d = 2×10¹⁸ cm^-3) on a 500-nm-thick p-In_0.52Al_0.48As (N_a = 8×10¹⁵ cm^-3) barrier was grown by metal organic vapour-phase epitaxy (MOVPE) on a p+-InP wafer (Fig. 1 (a)). In order to form a channel for the JL devices, the In_0.53Ga_0.47As layer was thinned using a 10% H₂O₂/10% HCl digital wet etching process to achieve channel thicknesses of 24, 20 and 16 nm. A gate enclosed device layout was employed to simplify the fabrication process flow (Fig. 1(b-e)). A surface passivation in 10% (NH₄)₂S for 30 min was performed before atomic layer deposition (ALD) of an 8.5-nm-thick Al₂O₃ gate oxide. A Pd gate was formed by e-beam evaporation and lift-off. The Al₂O₃ on the S/D contact areas was etched in dilute HF. The S/D contact formation was performed by e-beam evaporation of a Au/Ge/Au/Ni/Au stack and lift-off. The RFPT (13.6 MHz) was performed in forming gas (10%H₂+90%N₂) with additional heating of the sample holder (up to 200°C). Temperature of the samples at the RFPT did not exceed 250°C [2].

Well behaved I_d-V_g characteristics measured on the 24-nm-thick In_0.53Ga_0.47As channel device are shown in Fig. 2. A threshold voltage (V_T) of -0.55 V was extracted using the second-derivative method. Scaling the In_0.53Ga_0.47As channel thickness down to 16 nm improved the subthreshold swing (SS) but degraded the maximum I_d and I_ON/I_OFF due to the combined effect of S/D series resistance (RSD) and mobility degradation. As a result, the lowest SS value (115 mV/dec) was extracted on the 16-nm-thick In_0.53Ga_0.47As channel device and 190 mV/dec - on the 24-nm-thick In_0.53Ga_0.47As channel one, but the highest I_ON/I_OFF value (1.5×10⁵) was obtained on the 20-nm-thick In_0.53Ga_0.47As channel device and 2.0×10⁴ - on the 24-nm-thick In_0.53Ga_0.47As channel one. The gate-to-channel C_gc-V_g characteristic featured a low frequency dispersion near the accumulation region, suggesting a low density of interface traps (D_it) in the upper part of the In_0.53Ga_0.47As bandgap. Moreover, the conductance analysis yielded low D_it values ranging from 1.5×10¹² to 3.5×10¹² cm^-2×eV^-1 from the conductance band edge to midgap, correspondingly. Measurements of RSD on circular transfer length method (CTLM) structures yielded the value of 12 kOhm on the 20-nm-thick In_0.53Ga_0.47As channel devices and contacts were strongly rectifying. RF plasma treatment with power 0.5 W/cm² at 150°C resulted in Ohmic SD contact, a strong decrease of RSD down to 45 Ohm (Fig. 3) and increases the I_ON by two orders of magnitude (Fig. 2). Additionally, SS for the plasma treated devices decreases from 190 mV/dec to 150 mV/dec, and the threshold voltage shifts to positive values by 0.4 V (Fig.2). This is associated, correspondingly, with a decrease of D_it and negative charge in the gate dielectric. The conductance analysis yielded reduction of D_it at midgap down to 1.0×10¹² cm^-2×eV^-1.

[1] Colinge J.-P., Lee C.-W., Afzalian A., Akhavan N.D., Yan R., Ferain I., Razavi P., O'Neill B., Blake A., White M., Kelleher A.-M., McCarthy B., Murphy R. Nanowire Transistors Without Junctions. Nature Nanotechnology. Vol. 5, P. 225-229 (2010).

[2] Nazarov A.N., Lysenko V.S., Nazarova T.M. Hydrogen Plasma Treatment of Silicon Thin-film Structures and Nanostructured Layers. Semiconductor Physics, Quantum Electronics & Optoelectronics. Vol. 11, P. 101-123 (2008).