At the end of the traditional scaling of CMOS technologies, the industry started to explore paths to push for more performance in chips. This was and has always been driven by the performance-hungry high-end CPU and GPU manufacturers. The main approach was to increase the gate area per chip area by using 3D transistors instead of planar ones, i.e. FinFET. These Fins are very thin, so that in addition to the “double” gate area, the whole conducting channel becomes fully depleted. This reduces the short channel effects dramatically and thus enables a significant shrink of the channel length. However, the manufacturing of FinFET CMOS turned out to be very complex and thus costly. It took the industry more than 10 years to introduce it, first time at the 22nm node in 2011 [1]. Due to this non-planar device architecture, the chip design became much more complex so that only few design houses could afford it.

In the last few years, a new trend emerged in semiconductor industries: Connecting everything with everything, also called the Internet of Things (IoT). For this space of applications, computing power does not matter as much as low leakage and/or low dynamic power at low cost.

With 22FDX, GLOBALFOUNDRIES offers a technology with less complexity than FinFET, same gate length scaling due to fully-depleted channels, and additional features like back-gate biasing which perfectly suits the IoT market needs [2].

This technology offers nFET (pFET) drive currents of 910µA/µm (856µA/µm) at 0.8V and 100nA/µm leakage. It can be extended down to pA/µm transistor and pA/bitcell leakages for ultra-low leakage applications and below 0.4V Vdd operation for ultra-low dynamic power applications. At the same time, it offers RF/analog characteristics superior to FinFET with fT/fMAX of 375GHz/290GHz and 260GHz/250GHz for nFET and pFET, respectively, which serves a huge range of RF and millimeter wave applications.

22FDX also offers a competitive SRAM bitcell with competitive 1.46mV-μm FinFET-like transistor mismatch coefficient (AVt). Extremely low minimum operating voltages (Vmin) are reported for both the high-density (HD) 0.110μm2 and high-current (HC) 0.124μm2 bitcells without any assist, showing 95% limited yield (LY) Vmin values of 0.6V and 0.5V for 64Mb HD and 128Mb HC arrays, respectively [3].

The co-integration of SOI and bulk devices on the same wafer expands the device suite to very efficient diodes, bipolar devices, capacitors, and LDMOS.

Main features are FDSOI substrate for nFET, SiGe channel for pFET and dual in-situ doped raised source/drain epitaxy. Despite the utilization of the majority of process steps from the 28nm technologies, a logic/SRAM die scaling of 0.72x/0.83x relative to the 28nm technology node is achieved. All of the above combined enables cost-efficient manufacturing.

Back-gate biasing is a unique feature in FDSOI technologies which allows altering the I/V curves of individual devices up to whole blocks of circuitry to boost performance or minimize leakage wherever needed. This feature gives an additional degree of freedom to circuit and chip designers to optimize their products. Some examples will be shown.

Furthermore, GLOBALFOUNDRIES is in development of 12FDX, the next FDSOI technology node, which offers further area scaling at enhanced performance and extended features.

References:

[1] C. Auth et al., VLSIT, p.131-132 (2012)

[2] R. Carter et al., IEEE International, p. 2.2.1 - 2.2.4 (2016)

[3] V. Joshi et al., VLSIT, p.222-223 (2017)