The introduction of chemical vapor deposition (CVD) diamond as a viable substrate for GaN HEMTs [1], [2] makes GaN-on-diamond an attractive means to run higher power densities through the GaN HEMT compared to traditional GaN on host substrates. While power densities of 20 and 40W/mm have been demonstrated for pulsed devices on silicon carbide (SiC) [3], continuous powers exceeding 10W/mm will reduce the lifetime of the GaN HEMTs due to self-heating. GaN-on-diamond holds a promise of reducing the problems associated with self-heating and allows for increases in the power density of HEMT devices. To date, GaN-on-diamond has been shown to allow for higher areal power densities than GaN-on-SiC [4], [5]. The process of making GaN-on-diamond was first demonstrated more than 10 years ago [1], [2] has evolved and improved over the years from broken samples 1cm on a side with a 25 micron (800 W/mK thermal conductivity) diamond substrate to a 4” process with a 100 micron (1500 W/mK) diamond substrate. In this paper we will look at wafer level electrical comparisons of GaN-on-diamond to GaN on host substrates and at process monitoring for the 100 GaN-on-diamond wafers.

The process we use to make GaN-on-diamond is to transfer an epitaxial layer of GaN from a silicon substrate to diamond. In this process we flip the GaN grown on silicon onto a sacrificial substrate and remove the growth silicon. At this point the AlGaN transition layers (TLs) which are necessary to grow low defect density GaN on silicon are etched away. The TLs while critical to the growth of low defect GaN are themselves highly defective and have poor thermal properties [6]. It is therefore advantageous both electrically and thermally to remove these layers. Once the TLs are removed we protect the GaN back side with a nucleation/adhesion layer and we grow the CVD diamond.

The standard metric for GaN-on-diamond is the thermal boundary resistance (TBR) which measures how efficiently the heat can be transferred from the GaN to the diamond. With collaborators we have been able to demonstrate a drop from 135 m²K/GW to as low as 10 m²K/GW by removing the TLs and maintaining a consistent adhesion layer thickness of silicon nitride between the GaN and the diamond [7]. Process monitoring shows that we can consistently maintain a 35 +/- 5nm SiN adhesion layer between the GaN and the diamond. In this paper we will present process monitoring data of this and other parameters for the last 100 GaN wafers.

Less well established are the electrical metrics for comparing GaN-on-diamond to GaN on host substrates. One important metric of electrical performance for GaN-HEMTs is the flat capacitance at high reverse bias. It allows us to characterize the presence of traps and/or doping at the GaN to host interface [8]. In our case the GaN to diamond interface. We measure this flat capacitance by taking the capacitance voltage (C-V) profile. Results show that we can take GaN-on-silicon which has a flat band capacitance of 25pF and turn it into GaN-on-diamond with a flat band capacitance of ~ 2pF Figure[1a]. This low capacitance is indicative of negligible GaN buffer and epi interface charge/doping. The capacitance of the GaN-on-diamond is now comparable to GaN-on-silicon carbide Figure [1b].