The need of a low-power, fast and low-cost CMOS compatible embedded DRAM cell is rising incessantly with the upcoming Internet of Things (IoT) era [1]. Capacitor-less DRAM cells [2, 3] have emerged as a promising solution since they do not require dedicated fabrication steps to deal with the storage node. Among this breeze of cells, the MSDRAM [4] can be highlighted due to the simpler manufacturing process.

The MSDRAM (Meta-Stable-Dip RAM) memory operation is based on inter-gate coupling [5] and non-equilibrium state [6]. The back gate (ground-plane) is biased positively to induce a virtual n-type back-channel while the front-gate voltage is negative to retain any available hole in the body. By modulating the hole population at the front-channel, the vertical top-gate induced electric field is screened (or not) so that the back electron-channel is maintained (or depleted). Depending upon the back-channel depletion degree different conductance values are achieved defining the logic ‘1’ and ‘0’ memory states. State programming is carried out by injecting holes by band-to-band tunneling at the drain edge (W₁) or evacuating holes by top-gate capacitive coupling (W₀)

In this work, a III-V InGaAs MSDRAM cell is built and its memory operation is demonstrated by TCAD numerical simulations in Synopsys [7, 8]. The detailed structure and the doping are shown in Fig.1. The basic memory operation is depicted in Fig. 2a for a W₀-R-W₁-R-W₀-R sequence with W_1/0 being the ‘1’/’0’ state programming and R the reading. The current after any W₀ operation remains much lower than after W₁. Figure 2b represents the body electron and hole densities after the first W₀ and W₁, respectively. Following W₀, the hole density is limited underneath the top dielectric allowing a strong vertical field that depletes the back-channel from electrons leading to a drastic drop in the conductance and thus in the drain current. On the contrary, after generating holes by band-to-band tunneling during W₁, the electron back-channel is reinforced enabling a larger current level while reading afterward.

In conclusion, preliminary TCAD results demonstrate the feasibility of implementing the MSDRAM concept on III-V materials.

REMINDER project (No 687931) is thanked for support.