Introduction: In the past few years junctionless nanowire MOSFETs appeared as one of the candidates for future technological nodes having great potential in digital and analog applications [1,2]. In these devices the fin height (H_FIN) and the fin width (W_FIN) have a strong influence on the electrostatic coupling that in turn becomes important for the I_ON/I_OFF ratio [3]. Fig.1 shows the cross-section of a junctionless nanowire transistor with its geometrical parameters. This work analyzes the effects of the fin height on the electrical parameters of junctionless transistors through experimentally calibrated 3-D simulations. Results show that for long channel devices the better compromise is obtained with higher fin height, with higher I_ON/I_OFF and smaller values of SS and DIBL, whereas for short channel ones the better compromise is found with smaller fin height, due to the reduced SS and DIBL and increased I_ON/I_OFF ratio.

Results: To study the effect of the H_FIN on these devices, simulations were made using Sentaurus TCAD from Synopsys. The simulations were calibrated with experimental data for long channel devices as a function of the W_FIN and extrapolated for a study with variable H_FIN. Fig. 2 shows the experimental and calibrated simulation for several W_FIN as a function of the gate voltage with a drain voltage of 50mV [4]. The simulated devices used doping concentration of 4.10¹⁸ cm^-3, Equivalent Oxide Thickness (EOT) of 1.38nm and work-function of 4.7eV. The box thickness of 150nm, W_FIN of 13nm and 18nm, variable H_FIN from 10nm to 60nm, channel length (L_G) of 100nm, 50nm and 30nm and channel extensions of 30nm. The devices have either doped extensions with 5.10²⁰cm^-3 (to reduce the series resistance (R_SD) [5]) or extensions with the same doping of the channel (referred as non-doped in this work). For these simulations, the crystallographic orientation of the device was considered and its effects on carrier mobility.

Fig. 3 shows the subthreshold slope (SS) as a function of H_FIN and one can see that doping the extension increase the SS for all devices, showing the degradation caused by short channel effects [6]. One can see that for long channel (L_G=100nm), the SS decreases as H_FIN is increased, while the opposite occurs to the short channel devices (L_G=30nm), i.e. the H_FIN reduction improves the SS. Fig. 4 shows the threshold voltage (V_TH) and the DIBL as a function of H_FIN. For devices tending to double-gate architecture (H_FIN>>W_FIN) the V_TH is weakly sensitive to H_FIN while for smaller H_FIN the V_TH increases due to the electrostatic coupling of the gate. The same occurs with the DIBL and the improvement on these devices comes from a smaller H_FIN.

Fig. 5 and Fig. 6 shows the On and Off currents (I_ON and I_OFF, respectively) as a function of H_FIN, respectively. The I_ON has been extracted at a gate voltage overdrive (V_GT) of 0.8V and I_OFF at V_GT=-0.3 V. The I_ON values were compensated by the effect of the R_SD. The use of doped extensions increase the I_ON, effect that is more pronounced on smaller H_FIN and L_G, whereas it induces a higher degradation on the I_OFF for short L_G than the long L_G. The devices with non-doped extensions have better I_OFF because of lower SS but the I_ON is much lower. Fig. 7 shows I_ON/I_OFF ratio as a function of the H_FIN. We can see that for L_G=100nm a higher I_ON/I_OFF ratio comes from the increase in H_FIN while for L_G=30nm the better ratio comes from the decrease in the H_FIN. It indicates that the better I_ON/I_OFF is obtained moving towards double-gate shape for long-channel devices to nanowire shape for short channel ones. Also, the L_G=50nm has values close to L_G=100nm, but for the doped extensions the device has tendency similar to the L_G=30nm.

Conclusions: For this work, we analyzed the main parameters of junctionless transistors with different H_FIN and the effects for short L_G with and without doped extensions shows a greater advantage with smaller H_FIN (nanowire), while for long L_G the advantage becomes more pronounced by the increase of H_FIN as the device tends to become double gate.

Acknowledgements: The authors acknowledge Sylvain Barraud, Maud Vinet and Olivier Faynot for providing the samples and the founding agencies CNPq, CAPES and FAPESP [grant #2016/10832-1].

References:

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[2] R. T. Doria et al. IEEE TED, 58,2511-2519,(2011)

[3] R. Yan et al. Microelectronics Reliability, 51,1166-1171,(2011).

[4] T. A. Ribeiro, et al. 32^nd SBMicro,1-4,(2017).

[5] C.-H. Park et al, SSE, 73,7–10,(2012).

[6] A. Cerdeira, et al. 30^th SBMicro,1-4,(2015).