In a first moment, to understand the strain/stress generation and relaxation effects along the integration we developed models based on Finite Element Method and identified the critical steps in the integration. We show that a major component of strain in the Si-channels is generated after dummy gates and spacers are done and the multilayer is recessed in the unprotected regions of the fin for the later fabrication of source and drain by epitaxy. At this step, the relaxation of the SiGe layers induce a tensile stress in the Si-channels as shown in the central image of Fig. 1a. A second important transition occurs at the step that characterizes the principal difference from SGAA with FinFET integration. It comes after the dummy gate is removes and the sacrificial SiGe layers are etched resulting in suspended Si-channels. According to our model, the tensile stress previously generated is significantly relaxed (right of Fig. 1a). However, a tensile characteristic tend to be present when the channels will be wrapped by the gate providing a favorable situation for NMOS but detrimental for PMOS.
In a second moment, we present our progress to validate, adjust or correct the proposed models based on experimental results. For this, we use geometric phase analysis and precession electron diffraction (PED) techniques of advanced transmission electron microscopy (TEM) to assess the strains with nanometer spatial resolution. The protocols needed for interpretation of the results and comparison with models will be discussed. Structures for SGAA fabricated in different substrates such as bulk-Si, virtually relaxed SiGe, strained Silicon-On-Insulator and compressive SiGe-On-Insulator are examined in this work.
As an example of our results and methodology, in Fig. 1b we display a dark-field TEM micrograph of a fin-patterned multilayer Si/SiGe on virtually relaxed SiGe substrate along the fin-direction. It is composed by a relaxed substrate Si0.8Ge0.2, a 50 nm thick Si layer (dark contrast) and the 10nm Si/7nm Si0.65Ge0.35 (bright contrast) multilayer ended by a top-layer of 17 nm Si0.65Ge0.35. Figures 1c corresponds to a map of the vertical strain εzz obtained by PED. Strain values are given with respect to the Si0.8Ge0.2 substrate taken as reference in the experiment. The Si layers have therefore a smaller lattice because of the tensile strain in the horizontal direction and the different composition of the layer with respect to the reference. The Si0.65Ge0.35 naturally present higher values due to the higher Ge content compared to Si0.8Ge0.2, but also due to an elastic reaction to the compressive horizontal strain associated to lattice mismatch. In Fig. 1d the results from model calculation of the structure considering the experimental spatial resolution and convolution effects for PED. The agreement with experiment allows the deconvolution of the map to present the real strain in the structure (Fig. 1e). The map in Fig. 1f shows the lattice rotations in the structure. The top portion of the stack rotates outward due to the predominant relaxation of the Si0.65Ge0.35. The bottom part rotates inward in association to the contraction of the Si layers.
A particularly interesting result considering SOI-type substrates will also be presented. We reveal that for compressive SiGe-On-Insulator the patterning process of the multilayer at room temperature induces stress relaxation by a gliding mechanism along the interface with the insulator. As a consequence, elastic energy is transferred to the Si layers creating high tensile uniaxial strain, a favorable configuration to improve the mobility of electrons in NFETs. The phenomenon is modelled and discussed in terms of its possible physical origin/mechanism.