Stress and Strain Evolution in Stacked Gate-All-Around Transistors for Sub-7nm Node Studied By Advanced Transmission Electron Microscopy Techniques and Finite Element Method Modelling
S. Reboh, R. Coquand (CEA, LETI, Minatec Campus, Université Grenoble Alpes), N. J. Loubet (IBM Research), N. Bernier (CEA, LETI, Minatec Campus, Université Grenoble Alpes), R. Chao (IBM Research), G. Audoit (CEA, LETI, Minatec Campus, Université Grenoble Alpes), J. L. Rouviere (CEA, INAC, Minatec Campus, Université Grenoble Alpes), S. Barraud (CEA, LETI), E. Augendre (Univ. Grenoble Alpes, CEA-LETI, MINATEC Campus), J. Li, R. Muthinti, J. Gaudiello (IBM Research), N. Gambacorti (CEA, LETI, Minatec Campus, Université Grenoble Alpes), T. Yamashita (IBM Research), and O. Faynot (Univ. Grenoble Alpes, CEA-LETI, MINATEC Campus)