The development of low-temperature polycrystalline silicon (LTPS) based on excimer laser annealing has realized CMOS TFTs with notable electrical performance; however, this method is not easily scalable to large area glass panel production. This need has led to recent interest in the application of flash-lamp annealing (FLA) for the LTPS crystallization process. Previous work in this field has demonstrated PMOS TFTs with encouraging carrier mobility [1], that are scalable to current flat panel display industrial standards and are compatible with a self-aligned gate structure to minimize parasitic capacitance [2]. Self-aligned devices demonstrate good operation at low drain bias (i.e. 1 V <|V_DS|<3 V), but suffer a loss of charge injection and gate modulation as drain biases increases, impeding both on-state and off-state behavior as shown in Figure 1. It is hypothesized that the low temperature limit for the activation of ion-implanted dopants on glass substrates leaves behind lateral end-of-range damage, resulting in localized areas of high defect density at the interface between source/drain and channel regions. This impedes transistor operation in two ways. Charge trapping prevents effective source injection at very low drain bias conditions (e.g. |V_DS|= 0.1 V), due to the low lateral field. At high drain bias these defects further limit source-channel charge injection, as well as degrade gate control in the off-state through a defect-assisted soft-GIDL mechanism.

This work focuses on a method of curbing this loss of charge injection and gate modulation by using techniques derived from electrostatic doping. The addition of secondary electrodes that partially overlap the channel region can act as polarity gates, independently tuning the Fermi level at the source-channel and channel-drain boundaries (see Figure 2). At the source this can assist carrier accumulation and trap saturation, helping facilitate charge injection into the channel. At the drain this can emulate the effects of a lightly-doped drain (LDD) region, thus suppressing drain leakage and allowing the device to shut off more effectively. These overlapping gate structures present a method to restore gate modulation without sacrificing all of the reduced capacitance benefits of the self-aligned configuration, and realize device operation that reflects the limitations of the channel quality without confounding factors.

[1] T. Mudgal, K. Bhadrachalam, P. Bischoff, D. Cormier, R.G. Manley, and K.D. Hirschman, “CMOS Thin-Film Transistors via Xe Flash-Lamp Crystallization of Patterned Amorphous Si,” ECS J. Solid State Sci. Technol. 6 (12) Q179-Q181 (2017) / DOI: 10.1149/2.0021802jss

[2] G. Packard, A. Rosenfeld, P. Bischoff, K. Bhadrachalam, V. Garg, R.G. Manley and K.D. Hirschman, “Integration challenges of flash lamp annealed LTPS for high performance CMOS TFTs”,ECS Trans. 86 (11), 57-72 (2018) DOI: 10.1149/08611.0057ecst