In this work, we perform electrothermal finite element simulations of reset and set operations on iPCM structures consisting of alternately stacked Ge2Sb2Te5 (GST) and GeTe layers using COMSOL multiphysics [7-10]. Electrical pulses are applied for reset and set processes utilizing an internal circuit model where a transistor is used as an access device. Coupled electric current and heat transfer physics are employed to incorporate Joule heating and thermoelectric effects (Thomson heat within a single material and Peltier heat at material interfaces) with temperature dependent Seebeck coefficients, thermal conductivities, electrical resistivities, heat capacities and thermal boundary resistances (TBR) for each material / material pairs. Latent heat of fusion is included in the amorphous-crystalline and solid-liquid transitions [10], giving rise to heat release at the crystal-amorphous boundaries during crystal growth and heat absorption at the grain boundaries during amorphization. Grain boundaries and material interfaces have high energy sites, making them easier to melt, described as heterogeneous melting [10].
iPCM [5] structures utilize engineered interfaces formed between nanometer scale thin-film stacks, promoting amorphization through increased number of material interfaces and reduced thermal conduction due to TBR. Furthermore, the melting temperature, electrical conductivity and Seebeck coefficient of the different materials within an iPCM device differ. Hence, such layered structures may have the advantage of melting of only one of the alternating layers assisted by local heating or cooling due to Peltier effect at the interfaces.
Our results on iPCM and conventional PCM structures of same dimensions and geometry (20 nm wide, 150 nm high pore-cells) show ~ 50% reduction in reset times and more consistent set times for iPCM cells due to lesser variations in grain sizes and location of boundaries.
Acknowledgment: This work is partially supported by the National Science Foundation under award DMR-1710468.
References:
[1] S. W. Fong et al., IEEE Trans. Electron Devices 64, 4374 (2017).
[2] G. W. Burr et al., IEEE J. Emerg. Sel. Topics Circuits Syst. 6, 146 (2016).
[3] J. Tominaga et al., physica status solidi (RRL) 13, 1800539 (2019).
[4], K. V. Mitrofanov et al., Japanese Journal of Applied Physics 57, 04FE06 (2018).
[5] K. L. Okabe et al., Journal of Applied Physics 125, 184501 (2019).
[6] T. Ohyanagi et al., AIP Advances 6, 105104 (2016).
[7] Z. Woods et al., IEEE Trans. Electron Devices 64, 4466 (2017).
[8] Z. Woods et al., IEEE Trans. Electron Devices 64, 4472 (2017).
[9] J. Scoggin et al., Applied Physics Letters 112, 193502 (2018).
[10] J. Scoggin et al., Applied Physics Letters 114, 043502 (2019).